Sony HCD-DP700 / MHC-DP700 Service Manual ▷ View online
57
HCD-DP700
Function
Pin Name
Pin No.
I/O
58
MOD0
I
Operation mode signal input (L : single chip mode, H : use prohibited)
59
EXLOCK
I
Lock signal input
60
VDDI
—
Power supply
61
VSS
—
Ground
62 - 66
A17 - A13
O
External memory address output (SRAM)
67
GP10
I/O
LRCK0
68
GP9 (DECODE)
O
DECODE
69
GP8 (AUDIO)
I
AUDIO
70
VDDI
—
Power supply
71
VSS
—
Ground
72 - 75
D15/GP7 - D12/GP4
I/O
External memory data input /output (general port)
76
VDDE
—
Power supply
77 - 80
D11/GP3 - D8/GP0
I/O
External memory data input /output (general port)
81
VSS
—
Ground
82 - 85
A9 - A12
O
External memory address output (SRAM)
86
TDO
O
Simple emulation data output
87
TMS
I
Simple emulation data input start, end terminal
88
XTRST
I
Simple emulation async BREAK signal input terminal
89
TCK
I
Simple emulation clock signal input
90
TDI
I
Simple emulation data input
91
VSS
—
Ground
92 - 97
A8 - A3
O
External memory address output (SRAM)
98, 99
D7, D6
I/O
External memory data input/output (SRAM)
100
VDDI
—
Power supply
101
VSS
—
Ground
102 - 105
D5 - D2
I/O
External memory data input/output (SRAM)
106
VDDE
—
Power supply
107, 108
D1, D0
I/O
External memory data input/output (SRAM)
109, 110
A2, A1
O
External memory address output (SRAM)
111
VSS
—
Ground
112
A0
O
External memory address output (SRAM)
113
PM
I
PLL initialization input terminal
114, 115
SDI3, SDI4
I
Audio IF data input
116
SYNC
I
Sync/async selection input (L : sync, H : async)
117 - 119
VSS
—
Ground
120
VDDI
—
Power supply
58
HCD-DP700
6-30.
IC BLOCK DIAGRAMS
IC101
CXD3017Q (BD BOARD)
IC102
BA5974FM-E2 (BD BOARD)
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
1
2
3
10 11 12 13 14 15 16 17 18
19
20
60
59 58 57
56
55
54
52
51
50
49
48
47
46 45 44
53
21
39
40
41
42
43
22
23
79
24
26
25
28
27
29
30
31
32
35
36
37
38
33
34
80
62
61
77
78
78
75
76
76
73
74
72
71
70
69
66
65
64
63
68
67
4
5
6
7
8
9
D/A
Interface
Digital
PLL
CPU
Interface
Digital
OUT
Serial-In
Interface
Over Sampling
Digital Filter
Timing
Logic
PWM
3rd-Order
Noise Shaper
PWM
Asymmetry
Corrector
A/D
Converter
OP Amp
Analog SW
Clock
Generator
Digital
CLV
MIRR
DFCT
FOK
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SELED
SERVO
EFM
Demodurator
Servo Auto
Sequencer
SERVO
Interface
Error
Corrector
16K
RAM
Sub Code
Processor
PWM
GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM
GENERATOR
SLED PWM
GENERATOR
SQSO
SQCK
XRST
DATA
XLAT
CLOK
SENS
SCLK
VDD
SPOA
SPOB
XLON
XPCK
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
TEST
TES1
VC
FE
SE
TE
CE
RFDC
ADIO
IGEN
ASYO
ASYI
BIAS
RFAC
CLTV
FILO
FILI
PCO
DOUT
XTAI
XTAO
AVDD1
AOUT1
AIN1
LOUT1
LOUT2
AIN2
AOUT2
LMUT
XVSS
RMUT
SYSM
ATSK
WFCK
XUGF
GFS
C2PO
VSS
XTSL
AVDD
AVSS
AVSS
AVDD
VSS
VDD
LRCK
PCMD
BCK
EMPH
XVDD
AVSS1
AVSS2
AVDD2
59
HCD-DP700
IC103
CXA2581N-T4 (BD BOARD)
10
11
12
4
3
EQ IN
9
D
10
F
E
8
C
7
B
6
A
AC SUM
DC_ OFST
RFDCI
11 RFDCO
VC
24 BST
25 VFC
CEI
EQ
APC
5
GND
AC
SUM
26 RFC
AC
VCA
23 RFG
22 VCC
20
21
CE
19 TE_BAL
18 TE
17 FEI
16 FE
1
LD
2
PD
11
SW 12
13
DVCC
14
DVC
15
RFAC
VC
EQ
ON/OFF
VC
VC
VC
VC
DVC
DVC
APC-OFF(Hi-Z)
RW/ROM
(H/L)
DVC
DVC
AVC
DVCC
VC
DVC
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
DVCC
VCC
VCC
VCC
VOFST
VOFST
VOFST
B
C
A
D
gm
gm
DVCC
IC302
µPC1330H (MAIN BOARD (1/3))
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1
CONT
GND
VCC
SW P2
GND
SW R2
IC11
LA1845 (MAIN BOARD (3/3))
ALC
AGC
REG
GND
VCC
AM
DET
STEREO
SW
P-DET
φ
VCO
304KHz
DECODER
ANTI-BRIDIE
PILOT
CANCEL
FF
38k
FF
19K
∠
PILOT
DET
AM
IF
AM
OSC
AM
MIX
AM/FM
AM
RF.AMP
COMP
BUFF
S-CURVE
IF
BUFF
LEVEL
DET
FM
IF
FM
DET
FM-IN
AM
MIX-OUT
REG
AM
IF-IN
GND
TUNED
STEREO
FM-DET
VCC
IF-REQ
MUTE
AM/FM
VCO
STOP
OSC
FM.SD
AM-AGC
S-METER
AFC
AM-RF
IN
DECODER
OUT
AM
DET-OUT
AM-OSC
DECODER
IN
PLL-IN
PILOT
CANCEL
R-OUT
L-OUT
π
2
FF
19K
∠0
TUNING
DRIVE
24
23
22
21
20
19
13
14
15
16
17
18
1
2
3
4
5
6
12
11
10
9
8
7
60
HCD-DP700
IC51
LC72131 (MAIN BOARD (3/3))
PHASE
DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16, 1/17 4BITS
12BITS
PROGRAMMABLE
DRIVER
UNIVERSAL
COUNTER
REFERENCE
DIVIDER
POWER
ON
RESET
1/2
CCB
INTERFACE
1
2 3 4 5
6 7 8 9
16
15
14
13
12
11
10
17
18
19
20
XOUT
VSS
AOUT
AIN
PD
VDD
FMIN
AMIN
XIN
DO
CL
DI
CE
IFIN
IO1
BO4
BO3
BO2
BO1
IO2
UNLOCK
DETECTOR
DATA SHIFT REGISTER LATCH
IC81
BU1924 (MAIN BOARD (3/3))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QUAL
R
D
ATA
VREF
VDD1
VSS1
MUX
VSS3
CMP
RCLK
XO
XI
(NC)
VDD2
VSS2
T1
T2
8TH SWITCHED
CAPACITOR
FILTER
PLL 57KHz
RDS/ARI
BIPHASE
DECODER
DEFFERENTIAL
DECODER
PLL
1187.5Hz
TEST
CLOCK
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