Sony HCD-CP100 / HCD-CP100K Service Manual ▷ View online
HCD-CP100/CP100K
31
31
6-18. SCHEMATIC DIAGRAM – POWER Board –
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
no mark : FM
The components identified by mark
0
or dotted
line with mark
0
are critical for safety.
Replace only with part number specified.
(Page 22)
HCD-CP100/CP100K
32
32
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTION
CORRECTION
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
• IC Block Diagrams
– CD Board –
– CD Board –
IC101
CXD2587Q
IC102
BA5974FP-E2
APC PD AMP
APC LD AMP
RF SUMMING AMP
RF EQ AMP
FOCUS ERROR AMP
TRACKING
ERROR AMP
VC BUFFER
VCC
50
µ
A
VEE
VEE
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCC
VEE
VCC
VEE
VEE
VC
VCC
LC/PD
LD ON
HOLD SW
AGC CONT
RFTC
RF I
RF O
RFE
TE
FE
RF BOT
HOLD
AGC VTH
LD
PD
A
B
C
D
VEE
F
E
VC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
+
–
–
VCC
+
–
–
+
–
–
+
–
–
+
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
IC103
CXA2568M-T6
33
HCD-CP100/CP100K
CH2/A CH2/B
NF
VCC
CG
NF
ALC
METAL
OUT
PRE
OUT
OUT
TAPE A
/TAPE B
REC
OUT
OUT
REC
IN
CH1/A CH1/B
NF
GND1
M/H
NF
CH2
CH2
ALC
M/N
CH1
GND
GND
CH1
+
–
+
–
+
–
+
–
A/B
GND
METAL
OUT
PRE
OUT
OUT
MIX
OUT
REC
OUT
OUT
REC
IN
IREF
VREF2
VREF1
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN
–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–
VS
STBY
MUTE
NC
NC
+PWVS
OUT
–
PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
– MAIN Board –
IC101, 201
TDA7296
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
IC320
KA3082
– TC Board –
IC401
TA8189N
34
HCD-CP100/CP100K
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
IC804
BU1924F-E2
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