Sony HCD-BC150 / HCD-BC250 Service Manual ▷ View online
62
HCD-BC150/BC250
Pin No.
Pin Name
I/O
Description
189
DVSS
—
Terminal Ground
190
VFO13
O
Not used (open)
191
IDGATE
O
Not used (open)
192
DVDD3
—
Power Supply (+3.3V)
193
UPGATE
O
Not used (open)
194
WOBSI
O
Not used (open)
195
SDATA
I
DATA RF signal input from RF AMP (IC102)
196
SDEN
O
SDEN signal output to RF AMP (IC102)
197
SLCK
O
CLK RF signal output to RF AMP (IC102)
198
BDO
I
BOO signal input from RF AMP (IC102)
199
ADCVSS
—
Terminal Ground
200
ADIN
I
ADIN signal input from RF AMP (IC102)
201
RFSUBI
I
Not used (open)
202
TEZISLV
I
Tracking error zero crossing low pass input
203
TEI
I
TE signal input from RF AMP (IC102)
204
CSO
I
CSO signal input from RF AMP (IC102)
205
FEI
I
FE signal input from RF AMP (IC102)
206
RFLEVEL
I
PI signal input from RF AMP (IC102)
207
RFAPDC
I
RFRP signal input from RF AMP (IC102)
208
RFAPAC
I
RFRP signal input from RF AMP (IC102)
209
HRFZC
I
RFZC signal input from RF AMP (IC102)
210
PWMVREF
I
VIP4 signal input from RF AMP (IC102)
211
PWM2VREF
I
V2P8 signal input from RF AMP (IC102)
212
ADCVDD3
—
Power Supply (+3.3V)
213
RFOTSLVP
O
Not used (open)
214
RFOTSLVN
O
Not used (open)
215
RFIN
I
RFIN signal input from RF AMP (IC102)
216
RFIP
I
RFIP signal input from RF AMP (IC102)
63
HCD-BC150/BC250
• MAIN BOARD IC506 CXD9720BQ (DIGITAL AUDIO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.6V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
—
Power supply terminal (+2.6V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal output to the D/A converter
20
BCKO
O
Bit clock signal output to the D/A converter
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the D/A converter
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.6V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
64
HCD-BC150/BC250
Pin No.
Pin Name
I/O
Description
49
WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface
receiver
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
117
TST2
I
Not used
65
HCD-BC150/BC250
Pin No.
Pin Name
I/O
Description
118
GP11
I
Not used
119
TST3
I
Not used
120
VDDI
—
Power supply terminal (+2.6V)
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