Sony DSK-GTX999 / HCD-GTX999 Service Manual ▷ View online
HCD-GTX999
53
OSCILLATOR
1/2 VCC
AUTO
RESET
LPF1
MAIN
CONTROL
A/D
20KBIT
SRAM
LPF2
D/A
2
3
4
5
6
7
8
9
10
11
15
14
13
12
CLOCK
RESET
MO
MI
D1
DO0
DO1
VCC
16
NC
CLOCK
REF
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1IN
1
NC
LPF1OUT
OP1OUT
OP1IN
CC1
CC2
GND
VDD 2
OUT 1
GND 3
+
–
VREF
CD
5
NC
4
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
1
D4
2
D6
3
COM
4
D7
5
D5
6
INH
7
VEE
8
GND
9
C
10
B
11
A
12
D3
13
D0
14
D1
15
D2
16
VCC
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
LOGIC LEVEL
CONVER
TER
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
–
–
THERMAL
SHUT DOWN
OVER CURRENT
PROTECT
VDD
VCC
2
GND
3
NC
5
OUT
4
CTL
1
–
+
VREF
DRIVER
IC204 BA6956AN
IC910, 930 SI-8001FFE
IC104 M65850FP-E1
IC203 PST3629NR
IC205 TC74LVX4051FT
IC940 BA00BC0WCP-V5E2
HCD-GTX999
54
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
Q
Q
CLR
Q
Q
1A
1B
1 CLR
CEXT
2
2 REXT/CEXT
1Q
2Q
GND
VCC
1 REXT/CEXT
CEXT
1
1Q
2Q
2 CLR
2B
2A
IN1 1
BPF2OUT
15
BPF1OUT
16
RECOUT
17
BPF2OUT
20
IN2 2
BUF1OUT 3
BPF2IN1 4
BPF2IN2 5
BPF2IN2 5
BAND-PASS
FILTER
BPF3IN1 6
BPF3IN2 7
BPF3IN2 7
BAND-PASS
FILTER
BPF4IN1 8
BPF4IN2 9
BPF4IN2 9
GND 10
BAND-PASS
FILTER
DET
DET
BPF1IN2
19
BPF1IN1
18
BAND-PASS
FILTER
DET
BPF3OUT
14
DET
BPF4OUT
13
N.C.
12
V+
11
DET
– DISPLAY Board –
IC741 SN74LV123APWR
IC751 NJM2760V-TE2
HCD-GTX999
55
• IC Pin Function Description
USB MICOM BOARD IC2 D708E001BRFP266 (USB SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2, 3
EM_A (_18),
EM_A (_13)
O
Address signal output to the fl ash memory
4
CD-PO
O
Reset signal output to the digital servo "L": reset
5
MCK
-
Not used
6
VSS
-
Ground terminal
7
EM_A (_19)
O
Address signal output to the fl ash memory
8
CVDD
-
Power supply terminal (+1.2V)
9
BCKI
I
Bit clock signal input from the data buffer
10
DVDD
-
Power supply terminal (+3.3V)
11
D_RESET
O
Reset signal output to the data buffer, A/D converter, D/A converter,
USB interface and USB 2.0 hub controller "L": reset
USB interface and USB 2.0 hub controller "L": reset
12
LRCKI
I
L/R sampling clock signal input from the data buffer
13
VSS
-
Ground terminal
14
XRESET
I
Reset signal input from the system controller "L": reset
15
VSS
-
Ground terminal
16
CVDD
-
Power supply terminal (+1.2V)
17
CLKIN
I
System clock (22.5792MHz) input terminal
18
VSS
-
Ground terminal
19
TMS
-
Not used
20
CVDD
-
Power supply terminal (+1.2V)
21
XTRST
-
Not used
22
OSCVSS
-
Ground terminal
23
OSCIN
-
Not used
24
OSCOUT
-
Not used
25
OSCVDD
-
Power supply terminal (+1.2V)
26
VSS
-
Ground terminal
27
PLLHV
-
Power supply terminal (+3.3V)
28
TDI
-
Not used
29
TDO
-
Not used
30
VSS
-
Ground terminal
31
DVDD
-
Power supply terminal (+3.3V)
32
EMU (0)
-
Not used
33
CVDD
-
Power supply terminal (+1.2V)
34
EMU (1)
-
Not used
35
TCK
-
Not used
36
VSS
-
Ground terminal
37
EM_CAS
O
Column address strobe signal output to the SDRAM
38
EM_WE
O
Write enable signal output to the SDRAM, fl ash memory and USB interface
39
EM_WE_DQM (0)
O
Write enable signal output to the SDRAM
40
VSS
-
Ground terminal
41
EM_D (7)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
42
DVDD
-
Power supply terminal (+3.3V)
43
EM_D (6)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
44
CVDD
-
Power supply terminal (+1.2V)
45, 46
EM_D (5), EM_D (4)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
47
VSS
-
Ground terminal
48, 49
EM_D (3), EM_D (2)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
50
DVDD
-
Power supply terminal (+3.3V)
51, 52
EM_D (1), EM_D (0)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
53
CVDD
-
Power supply terminal (+1.2V)
54
VSS
-
Ground terminal
55, 56
EM_D (15), EM_D (14)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
57
CVDD
-
Power supply terminal (+1.2V)
58, 59
EM_D (13), EM_D (12)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
60
DVDD
-
Power supply terminal (+3.3V)
61
EM_D (11)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
HCD-GTX999
56
Pin No.
Pin Name
I/O
Description
62
VSS
-
Ground terminal
63, 64
EM_D (10), EM_D (9)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
65
CVDD
-
Power supply terminal (+1.2V)
66
EM_D (8)
I/O
Two-way data bus with the SDRAM, fl ash memory and USB interface
67
EM_WE_DQM (1)
O
Write enable signal output to the SDRAM
68
DVDD
-
Power supply terminal (+3.3V)
69
VSS
-
Ground terminal
70
EM_CLK
O
Clock signal output to the SDRAM
71
EM_CKE
O
Clock enable signal output to the SDRAM
72
VSS
-
Ground terminal
73
DVDD
-
Power supply terminal (+3.3V)
74 to 76
EM_A (11_12),
EM_A (9_10), EM_A (8_9)
O
Address signal output to the SDRAM and fl ash memory
77
CVDD
-
Power supply terminal (+1.2V)
78
VSS
-
Ground terminal
79
EM_A (7_8)
O
Address signal output to the SDRAM and fl ash memory
80
EM_A (6_7)
O
Address signal output to the SDRAM, fl ash memory and USB interface
81
DVDD
-
Power supply terminal (+3.3V)
82
VSS
-
Ground terminal
83, 84
EM_A (5_6),
EM_A (4_5)
O
Address signal output to the SDRAM, fl ash memory and USB interface
85
CVDD
-
Power supply terminal (+1.2V)
86
EM_A (3_4)
O
Address signal output to the SDRAM, fl ash memory and USB interface
87
VSS
-
Ground terminal
88, 89
EM_A (2_3),
EM_A (1_2)
O
Address signal output to the SDRAM, fl ash memory and USB interface
90
CVDD
-
Power supply terminal (+1.2V)
91
EM_A (0_1)
O
Address signal output to the SDRAM, fl ash memory and USB interface
92
DVDD
-
Power supply terminal (+3.3V)
93
EM_A (10_11)
O
Address signal output to the SDRAM and fl ash memory
94
EM_BA (1)/EM_A (_0)
O
Bank address signal output to the SDRAM, and address signal output to the fl ash memory
and USB interface
and USB interface
95
VSS
-
Ground terminal
96
EM_BA (0)
O
Bank address signal output to the SDRAM
97
EM_CS (0)
O
Chip select signal output to the SDRAM
98
EM_RAS
O
Row address strobe signal output to the SDRAM
99
VSS
-
Ground terminal
100
EM_CS (2)
O
Chip select signal output to the memory decoder
101
CVDD
-
Power supply terminal (+1.2V)
102
EM_RW
-
Not used
103
DVDD
-
Power supply terminal (+3.3V)
104
EM_OE
O
Output enable signal output to the fl ash memory and USB interface
105
B
O
Address decode signal output to the memory decoder
106
VSS
-
Ground terminal
107
A
O
Address decode signal output to the memory decoder
108
I2CO_SCL/BOOT
I/O
Two-way I2C serial clock signal bus with the system controller
109
VSS
-
Ground terminal
110
GPIO/BOOT
-
Not used
111
I2CO_SDA/BOOT
I/O
Two-way I2C serial data bus with the system controller
112
DVDD
-
Power supply terminal (+3.3V)
113
SDTI
I
Audio serial data input from the A/D converter and D/A converter
114
VSS
-
Ground terminal
115
SDTO_O
O
Audio serial data output to the A/D converter and D/A converter
116
BD_CLK
O
Serial data transfer clock signal output to the digital servo
117
BD_SENS
I
Internal status (SENSE) input from the digital servo
118
VSS
-
Ground terminal
119
BD_GAIN-SW
O
Gain switch signal output to the motor/coil driver
120
BD_XLAT
O
Serial data latch pulse output to the digital servo
121
BD_DATA
O
Serial data output to the digital servo
122
BD_SCOR
I
Sub-code sync (S0+S1) detection signal input from the digital servo
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