Sony DAV-SB300 / HCD-SB300 Service Manual ▷ View online
69
HCD-SB300
•
IC Pin Function Description
DMB07 BOARD IC207 ZIVA5X-C2F (DVD SYSTEM PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDDP
—
Power supply terminal (+3.3V)
2
HA1
O
Address signal output to the programmable ROM and address latch
3 to 11
HD15 to HD7
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
12
VDDP
—
Power supply terminal (+3.3V)
13
GNDP
—
Ground terminal
14 to 19
HD6 to HD1
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
20
VDDP
—
Power supply terminal (+3.3V)
21
GNDP
—
Ground terminal
22
HD0
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
23
HDTACK
I
Acknowledge signal input terminal for host data transfer Not used
24
HIRQ0
I
Interrupt signal input terminal Not used
25
WEH.UDS
O
Write enable host upper data strobe signal output to the programmable ROM
26
WEL.LDS
O
Write enable host lower data strobe signal output terminal Not used
27
HREAD
O
Output enable signal output to the programmable ROM
28
GPIO0
I
Check jig detection signal input terminal
29
GND
—
Ground terminal
30
VDD
—
Power supply terminal (+1.8V)
31
GND25
—
Ground terminal
32
VDD25
—
Power supply terminal (+3.3V)
33 to 42
MA9 to MA0
O
Address signal output to the SD-RAM
43
GND25
—
Ground terminal
44
VDD25
—
Power supply terminal (+3.3V)
45, 46
MA10,MA11
O
Address signal output to the SD-RAM
47, 48
BA1, BA0
O
Bank select signal output to the SD-RAM
49
MCS0
O
Chip select signal output to the SD-RAM
50
MCS1
O
Chip select signal output terminal Not used
51
MRAS
O
Row address strobe signal output to the SD-RAM
52
MCAS
O
Column address strobe signal output to the SD-RAM
53
MWE
O
Write enable signal output to the SD-RAM
54
GND25
—
Ground terminal
55
VDD25
—
Power supply terminal (+3.3V)
56
MCLK
O
Master clock signal output to the SD-RAM
57 to 60
MD0 to MD3
I/O
Two-way data bus with the SD-RAM
61
GND25
—
Ground terminal
62
MDQM0
O
Write mask signal output to the SD-RAM
63
VDD25
—
Power supply terminal (+3.3V)
64 to 71
MD6 to MD11
I/O
Two-way data bus with the SD-RAM
72
GND25
—
Ground terminal
73
MDQM1
O
Write mask signal output to the SD-RAM
74
VDD25
—
Power supply terminal (+3.3V)
75 to 78
MD12 to MD15
I/O
Two-way data bus with the SD-RAM
79
GND
—
Ground terminal
80
VDD
—
Power supply terminal (+1.8V)
81 to 84
MD16 to MD19
I/O
Two-way data bus with the SD-RAM
85
GND25
—
Ground terminal
70
HCD-SB300
Pin No.
Pin Name
I/O
Description
86
MDQM2
O
Write mask signal output to the SD-RAM
87
VDD25
—
Power supply terminal (+3.3V)
88 to 95
MD20 to MD27
I/O
Two-way data bus with the SD-RAM
96
GND25
—
Ground terminal
97
MDQM3
O
Write mask signal output to the SD-RAM
98
VDD25
—
Power supply terminal (+3.3V)
99 to 102 MD28 to MD31
I/O
Two-way data bus with the SD-RAM
103
GND25
—
Ground terminal
104
VDD25
—
Power supply terminal (+3.3V)
105
VCLK
O
Not used
106
XCK_I/O_SEL
O
Not used
107
VS
O
Wide control signal output terminal
108
I/P SW
O
Interlace/progressive selection signal output terminal Not used
109
CDSEL
O
Digital out signal selection signal output terminal Not used
110
MREQ
O
Audio muting on/off request signal output to the system controller “H”: muting on
111
VDDP
—
Power supply terminal (+3.3V)
112
GNDP
—
Ground terminal
113
MDI
O
Serial data output terminal Not used
114
MC
O
Serial data transfer clock signal output terminal Not used
115
ML
O
Serial data latch pulse signal output terminal Not used
116
HIRQ2
I
Busy signal input from the EEPROM
117
VDAC_4B
—
Ground terminal
118
VDAC_VDD4
—
Power supply terminal (+3.3V)
119
VDAC_4
O
Component video signal output to the video amplifier
120
VDAC_3B
—
Ground terminal
121
VDAC_VDD3
—
Power supply terminal (+3.3V)
122
VDAC_3
O
Component video signal output to the video amplifier
123
VDAC_2B
—
Ground terminal
124
VDAC_VDD2
—
Power supply terminal (+3.3V)
125
VDAC_2
O
Component video signal output to the video amplifier
126
VDAC_1B
—
Ground terminal
127
VDAC_VDD1
—
Power supply terminal (+3.3V)
128
VDAC_1
O
Component video signal output to the video amplifier
129
VDAC_0B
—
Ground terminal
130
VDAC_VDD0
—
Power supply terminal (+3.3V)
131
VDAC_0
O
Component video signal output to the video amplifier
132
VDAC_DVSS
—
Ground terminal
133
VDAC_DVDD
—
Power supply terminal (+3.3V)
134
VDAC_REFVDD
—
Power supply terminal (+3.3V)
135
VDAC_REF
I
Reference voltage input terminal
136
VDAC_REFVSS
—
Ground terminal
137
XVSS
—
Ground terminal
138
XOUT
O
Clock signal output terminal Not used
139
XIN
I
System clock signal (27 MHz) input from the clock generator
140
XVDD
—
Power supply terminal (+3.3V)
141
AVSS2
—
Ground terminal
71
HCD-SB300
Pin No.
Pin Name
I/O
Description
142
AVDD2
—
Power supply terminal (+3.3V)
143
AVDD1
—
Power supply terminal (+3.3V)
144
AVSS1
—
Ground terminal
145
VDD
—
Power supply terminal (+1.8V)
146
GND
—
Ground terminal
147
XCK
O
Audio system clock output to the A/D converter and digital audio processor
148
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital audio processor
149
BCK
O
Bit clock signal (2.8224 MHz) output to the digital audio processor
150
DATA0 (DM)
O
Audio data (for down mix) output terminal Not used
151
DATA1 (FLR)
O
Audio data (for front) output to the digital audio processor
152
VDDP
—
Power supply terminal (+3.3V)
153
GNDP
—
Ground terminal
154
DATA2 (SLR)
O
Audio data (for surround (rear)) output to the digital audio processor
155
DATA3 (CSW)
O
Audio data (for center and sub woofer) output to the digital audio processor
156
IEC958
O
S/PDIF signal output terminal Not used
157
DAI_DATA
I
Data input terminal Not used
158
DAI_BCK
I
Bit clock signal (2.8224 MHz) input terminal Not used
159
DAI_LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
160
I2C_CL
I/O
Two-way I2C clock bus with the system controller and mechanism controller
161
I2C_DA
I/O
Two-way I2C data bus with the system controller and mechanism controller
162
CS (ZIVA_E2P)
O
Chip select signal output to the EEPROM
163
RXD1
I
Serial data input terminal for check jig
164
TXD1
O
Serial data output terminal for check jig
165
WRITE_CTRL
(ZIVA_E2P)
O
Write control signal output to the EEPROM
166
GNDP
—
Ground terminal
167
VDDP
—
Power supply terminal (+3.3V)
168 to 171
SDDATA7 to
SDDATA4
I
Stream data signal input from the DVD decoder
172
GND
—
Ground terminal
173
VDD
—
Power supply terminal (+1.8V)
174 to 177
SDDATA3 to
SDDATA0
I
Stream data signal input from the DVD decoder
178
SDREQ
O
Serial data request signal output to the DVD decoder
179
SDEN
I
Serial data enable signal input from the DVD decoder
180
GNDP
—
Ground terminal
181
VDDP
—
Power supply terminal
182
SDERROR
I
Serial data error signal input from the DVD decoder
183
SDCLK
I
Serial data transfer clock signal input from the DVD decoder
184
HIRQ1
I
Interrupt request signal input from the mechanism controller
185
DRVCLK
I
Serial data transfer clock signal input from the mechanism controller
186
DRVTX
I
Serial data input from the EEPROM and mechanism controller
187
DRVRX
O
Serial data output to the EEPROM and mechanism controller
188
DRVRDY
I
Ready signal input from the mechanism controller
189
VNW
—
Power supply terminal (+5V)
190
ALE
O
Latch enable signal output to the address latch
191
RST_SPC
O
Reset signal output to the mechanism controller “L”: reset
72
HCD-SB300
Pin No.
Pin Name
I/O
Description
192
INT/EXT
O
Internal/external selection signal output terminal
193, 194
HCS2, HCS1
O
Chip select signal output terminal Not used
195
HCS0
O
Chip select signal output to the programmable ROM
196
VDDP
—
Power supply terminal (+3.3V)
197
TRST
I
Reset signal input terminal (for JTAG)
198
TDO
O
Data output terminal (for JTAG)
199
TDI
I
Data input terminal (for JTAG) Not used
200
TMS
I
Mode selection signal input terminal (for JTAG)
201
TCK
I
Clock signal input terminal (for JTAG)
202
RESET
I
System reset signal input from the system controller “L”: reset
203
BUS CLK
O
Not used
204
GND
—
Ground terminal
205
VDD
—
Power supply terminal (+1.8V)
206
HA3
O
Address signal output to the programmable ROM
207
HA2
O
Address signal output to the programmable ROM and address latch
208
GNDP
—
Ground terminal
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