Sony DAV-SA35K / HCD-SA35K Service Manual ▷ View online
73
HCD-SA35K
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
I/O
O
—
—
O
O
O
I
I
I
I/O
I/O
O
I
O
O
—
—
I
I
I
I
—
—
I
I
I
I
O
I
—
—
I
I
I
I
I
O
I
—
O
O
O
O
I/O
O
—
I
O
I
I
Pin Name
DATA1(FLR)
VDDP
GNDP
DATA2(SLR)
DATA3(CSW)
IEC958
DAI_DATA
DAI_BCK
DAI_LRCK
I2C_CL
I2C_DA
CS(ZIVA_E2P)
RXD1
TXD1
WRITE_CTRL(ZIVA_E2P)
GNDP
VDDP
SDDATA7
SDDATA6
SDDATA5
SDDATA4
GND
VDD
SDDATA3
SDDATA2
SDDATA1
SDDATA0
SDREQ
SDEN
GNDP
VDDP
SDERROR
SDCLK
HIRQ1
DRVCLK
DRVTX
DRVRX
DRVRDY
VNW
ALE
RST_SPC
INT/EXT
HCS2
HCS1
HCS0
VDDP
TRST
TDO
TDI
TMS
Description
Audio data(Front L/R signal) output
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Audio data(Rear L/R signal) output
Audio data(Center/Subwoofer signal) output
S/PDIF signal (not used)
Data input from ADC (not used)
BCK signal input from ADC (not used)
LRCK signal input from ADC (not used)
I2C clock bus
I2C data bus
Chip select signal output to the EEPROM (IC204)
Serial data input for check jig
Serial data output for check jig
Write control signal output to the EEPROM (IC204)
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data7 input
SDBus data6 input
SDBus data5 input
SDBus data4 input
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
SDBus data3 input
SDBus data2 input
SDBus data1 input
SDBus data0 input
SDBus data request signal output
SDBus data enable signal input
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data error signal input
SDBus data clock input
Interrupt signal input from the mechanism controller (IC901)
Serial data clock input from the mechanism controller (IC901)
Serial data input from the mechanism controller (IC901) and the EEPROM (IC204)
Serial data output to the mechanism controller (IC901) and the EEPROM (IC204)
Ready signal input from the mechanism controller (IC901)
Power supply for 5V tolerance voltage input
Latch enable signal output for address data demux
Reset signal output to the mechanism controller (IC901)
Input selection signal output for SDBus or ADC
Chip select signal output for Medusa (not used)
Not used
Chip select signal output to the external ROM (IC206)
Power supply terminal (+3.3V) (I/O signal)
Reset signal input
Data output
Data input
TMS signal input
74
HCD-SA35K
Pin No.
201
202
203
204
205
206
207
208
I/O
I
I
I/O
—
—
I/O
I/O
—
Pin Name
TCK
RESET
BUS CLK
GND
VDD
HA3
HA2
GNDP
Description
TCK signal input
ZIVA reset input
Not used
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
Address bus 3
Address bus 2
Ground terminal (I/O signal)
75
HCD-SA35K
• IC701 CXD1882R (DVD DECODER)(DMB03 BOARD)
Pin No.
1, 2
3
4
5
6
7
8
9 to 14
15
16
17
18
19
20, 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
I/O
—
I/O
I
—
I
—
I
—
O
I
I
I
O
—
I
O
—
O
O
—
O
O
O
O
—
O
O
—
O
—
O
O
O
—
O
O
O
O
—
O
O
—
O
—
I
O
O
I
Pin Name
D5, D6
VSS
D7
A0
VDD
A1
VDD5V
A2 to A7
VSS
XWAIT
XRD
XWR
XCS
XINT0, XINT1
VDD
XHRS
HDB7
VSS
HDB8
HDB6
VDDS
HDB9
HDB5
HDBA
HDB4
VSS
HDBB
HDB3
VDD
HDBC
VDDS
HDB2
HDBD
HDB1
VSS
HDBE
HDB0
HDBF
XSAK
VDDS
XDCK
XSHD
VDD
REDY
VSS
XSRQ
HINT
XS16
HA1
Description
Two-way data bus with the mechanism controller
Ground terminal (digital system)
Two-way data bus with the mechanism controller
Address signal input from the mechanism controller
Power supply terminal (+3.3V) (digital system)
Address signal input from the mechanism controller
Power supply terminal (+5V)
Address signal input from the mechanism controller
Ground terminal (digital system)
Wait signal output terminal Not used
Read strobe signal input from the mechanism controller
Write strobe signal input from the mechanism controller
Chip select signal input from the mechanism controller
Interrupt signal output to the mechanism controller
Power supply terminal (+3.3V) (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Error flag signal output to the DSD decoder and DVD system processor
Stream data signal output to the DSD decoder and DVD system processor
Power supply terminal (+5V) (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Power supply terminal (+3.3V) (digital system)
Not used
Power supply terminal (+5V) (digital system)
Stream data signal output to the DSD decoder and DVD system processor
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Not used
Serial data effect flag signal output to the DSD decoder and DVD system processor
Power supply terminal (+5V) (digital system)
Serial data transfer clock signal output to the DSD decoder and DVD system processor
Header flag signal output to the DSD decoder
Power supply terminal (+3.3V) (digital system)
Not used
Ground terminal (digital system)
“DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder”
SACD mode: Serial data request signal input from the DSD decoder”
Not used
Not used
Not used
76
HCD-SA35K
Pin No.
57
58
59, 60
61
62, 63
64
65
66 to 69
70
71
72
73 to 75
76
77
78
79, 80
81
82 to 87
88
89
90
91
92
93
94
95
96, 97
98
99
100
101, 102
103
104 to 106
107
108
109
110
111
112
113, 114
115
116
117
118, 119
120
121
122, 123
124
125
126, 127
Pin Name
XPDI
VDDS
HA0, HA2
VSS
HCS0, HCS1
VDD
DASP
MDB0 to MDB3
VSS
MDB4
VDD5V
MDB5 to MDB7
XMWR
VDD
XRAS
MA0, MA1
VSS
MA2 to MA7
VDD
MA8
VSS
MA9
MNT1
MNT2
XMOE
XCAS
MDB8, MDB9
VSS
MDBA
VDD
MDBB, MDBC
VDD5V
MDBD to MDBF
GFS
VSS
APEO
VDD
DASYO
GNDA5
ASF1, AFS2
DASYI
RFDCC
RFIN
VCCA5, VCCA4
VCOR1
VCOIN
GNDA4, GNDA3
LPF5
VC1
LPF2, LPF1
I/O
I/O
—
I
—
I
—
I/O
I/O
—
I/O
—
I/O
O
—
O
O
—
O
—
O
—
O
O
O
O
O
I/O
—
I/O
—
I/O
—
I/O
O
—
O
—
O
—
—
I
I
I
—
—
I
—
O
I
I
Description
Not used
Power supply terminal (+5V) (digital system)
Not used
Ground terminal (digital system)
Not used
Power supply terminal (+3.3V) (digital system)
Not used
Two-way data bus with the D-RAM
Ground terminal (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+5V)
Two-way data bus with the D-RAM
Write enable signal output to the D-RAM
Power supply terminal (+3.3V) (digital system)
Row address strobe signal output to the D-RAM
Address signal output to the D-RAM
Ground terminal (digital system)
Address signal output to the D-RAM
Power supply terminal (+3.3V) (digital system)
Address signal output to the D-RAM
Ground terminal (digital system)
Address signal output to the D-RAM
EEPROM ready signal output to the mechanism controller
Operation clock signal output for PSP physical disc mark detection to DSD decoder
Output enable signal output to the D-RAM
Column address strobe signal output to the D-RAM
Two-way data bus with the D-RAM
Ground terminal (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+5V)
Two-way data bus with the D-RAM
Guard frame sync signal output to the mechanism controller
Ground terminal (digital system)
Absolute phase error signal output
Power supply terminal (+3.3V) (digital system)
RF binary signal output
Ground terminal (analog system)
Filter connected terminal for selection the constant asymmetry compensation
Analog signal input after integrated from the RF binary signal
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
RF signal input from the DVD/CD RF amplifier
Power supply terminal (+3.3V) (analog system)
VCO oscillating range setting resistor connected terminal
VCO input terminal
Ground terminal (analog system)
Signal output from the operation amplifier from PLL loop filter
Middle point voltage (+1.65V) input terminal
Inverted signal input to the operation amplifier from PLL loop filter
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