Sony DAV-LF1 / SA-TSLF1 Service Manual ▷ View online
22
22
SA-TSLF1
SA-TSLF1
•
IC Block Diagrams
– DIAT AMP Board –
IC101 XC62HR1502MR
+
–
–
3
OUTPUT
CONTROL
REFERENCE
VOLTAGE
4
1
2
5
CURRENT
LIMIT
NC
VIN
CE
VSS
VOUT
IC102 CXD4017R
ADVRH 6
VSS 5
VDDE 4
TEST14 3
TEST13 2
TEST12 1
ADAVS 7
ADAVD 8
ADVRL 9
ADVIN 10
VDDEE 11
VSS 12
XRST 13
DIFM0 14
DIFM1 15
TEST15 16
A/D
CONVERTER
BUFFER
RAM
ERROR
CORRECTOR
OUTPUT
INTERFACE
DEMODULATOR
PLREF
17
TEST16
19
APVCI
20
VSS
21
APCPO
22
APAVD
23
APAVS
24
APX
31
EXTCK
32
VSS
25
VDDI
26
VDDE
27
VCOR
28
CHNUM
29
DIVCODE
30
PLVAR
18
PLL
CLOCK
SELECTOR
CONTROLLER
CSOD
33
SRDT
34
SWDT
35
XSCEN
36
SCLK
37
SCMODE
38
OSCI
40
TEST0
44
TEST1
45
TEST2
46
TEST3
47
TEST4
48
OSCO
43
VSS
39
VDDE
41
VSS
42
CLOCK
GENERATOR
TEST11
64
EMPFS1
63
EMPFS0
62
DTVALID
61
DAOUT
60
LRCK
59
VDDI
58
VSS
57
VDDE
56
BCK
54
TEST10
55
TEST9
53
TEST8
52
TEST7
51
TEST6
50
TEST5
49
IC104 TK11225CMCL-G
1
2
3
6
4
CONT
GND
NP
VIN
5
GND
VOUT
CONTROL
CIRCUIT
BANDGAP
REFERENCE
CONSTANT
CURRENT
SOURCE
OVER HEAT &
OVER CURRENT
PROTECT
IC110, 112 CXD9774M
RESET 4
GND 1
GND 3
PWM BP 2
DREG RTN 5
GVDD 6
M3 7
M1 10
M2 11
DVDD 12
DREG 8
DGND 9
DGND 14
GND 16
GND 18
PWM
RECEIVER
TIMING
CONTROL
&
PROTECTION
SD 13
OTW 15
DIGITAL
REGULATOR
PROTECTION
LOGIC
OT
&
UVP
DVDD DREG
DREG
DGND
PWM AP 17
PWM
RECEIVER
DVDD DREG
DGND
DREG
GVDD
DREG
GATE
DRIVE
GVDD B
35
GVDD B
36
BST B
33
PVDD B
32
PVDD B
31
OUT B
30
OUT B
29
GND
28
GND
34
GATE
DRIVE
OCH
OCL
TIMING
CONTROL
&
PROTECTION
DREG
GATE
DRIVE
GVDD A
20
GVDD A
19
BST A
22
PVDD A
23
PVDD A
24
OUT A
25
OUT A
26
GND
27
GND
21
GATE
DRIVE
OCH
OCL
GVDD
GVDD
IC113 NJM2870F18 (TE2)
5
VIN
4
VOUT
2
GND
3
NOISE
BYPASS
1
CONTROL
BANDGAP
REFERENCE
THERMAL
PROTECTION
23
SA-TSLF1
IC901 STR-W6735N (US, CND, TW, MX)
IC901 STR-W6765N (EXCEPT US, CND, TW, MX)
IC901 STR-W6765N (EXCEPT US, CND, TW, MX)
IC904 NJM2374AE (TE2)
D 1
NC 2
S/GND 3
VCC 4
SS/OLP 5
FB 6
OCP/BD 7
DELAY
Q
R
S
+
–
+
–
+
–
Q
S
R
+
–
BOTTOM
SELECTOR
COUNTER
OSC
R
Q
S
SOFT START
+
–
OVP
REGULATOR
& ICONST
+
–
BURST
CONTROL
START/STOP
BURST
PROTECTION
LATCH
DRIVE
REGULATOR
OLP
BSD
BD
OCP
FB
CS 1
ES 2
CT 3
IN+
5
Q
S
R
PWM
LOGIC
OSC
GND 4
V+
6
VREF
+
–
+
–
+
–
ERROR AMP
PWM
COMPARATOR
SI
7
CD
8
IPK SENSE
– DIAT POWER Board –
Ver. 1.1
24
SA-TSLF1
• IC Pin Function Description
• DIAT AMP BOARD IC107 MB89537APFM-G-565-BNDE1 (SURROUND AMP CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used
2
MOD2
I
Setting terminal for the CPU operation mode Fixed at “L” in this set
3, 4
NC
O
Not used
5
MODEL
I
Setting terminal for the model
6
SIMUKE
I
Setting terminal for the destination
7 to 10
NC
O
Not used
11
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
12
AVR
I
Reference voltage (+3.3V) input terminal (for A/D converter)
13
AVSS
—
Ground terminal (for A/D converter)
14
DTVAILD
I
Data valid flag input from the RF demodulator “L”: invalid, “H”: valid
15
CSOD
I
Captor start delay signal input from the RF demodulator “H” active
16
NC
I
Not used
17
AC CUT
I
AC cut detection signal input terminal “L”: AC cut
18
NC
I
Not used
Reset signal input terminal “L”: reset
19
RESET
I
For several hundreds msec. after the power supply rises, “L” is input, then it
changes to “H”
20, 21
MD0, MD1
I
CPU operation mode setting signal input terminal
22
X0
I
Main system clock input terminal (8 MHz)
23
X1
O
Main system clock output terminal (8 MHz)
24
VSS
—
Ground terminal
25
FS2_EX
I
Not used
26
XRST_INIT
O
Reset signal output to the RF demodulator and stream processor “L”: reset
27, 28
NC
O
Not used
29
P23
I
Setting terminal for the CPU operation mode Fixed at “L” in this set
30
P22
I
Setting terminal for the CPU operation mode Fixed at “H” in this set
31, 32
NC
O
Not used
33
DAMP_PGMUTE
O
PG muting on/off control signal output to the stream processor “L”: muting on
34
DAMP_SOFTMUTE
O
Soft muting on/off control signal output to the stream processor “L”: muting on
35
DAMP_NSPMUTE
O
NSP muting on/off control signal output to the stream processor “L”: muting on
36
NC
O
Not used
37
DRIVE_RST
O
Reset signal output to the power driver “L”: reset
38
DRIVE_OCP
I
Shut down state input from the power driver “L”: shut down
39
DRIVE_OTW
I
Overtemperature warning signal input terminal Not used
40
P10
I
Setting terminal for the CPU operation mode Fixed at “H” in this set
41
LED_RED
O
LED drive signal output of the POWER indicator “H”: LED on
42
LED_GRN
O
LED drive signal output of the ON LINE indicator “H”: LED on
43 to 47
NC
O
Not used
48
SCMODE
O
Control mode selection signal output to the RF demodulator
“L”: pin setting, “H”: serial setting”
49
NC
—
Not used
50
XSCEN
O
Serial interface enable signal output to the RF demodulator
51
DIAT_SCLK
O
Serial interface data clock signal output to the RF demodulator
52
DIAT_SWDT
O
Serial interface data write signal output to the RF demodulator
53
DIAT_SRDT
I
Serial interface data read signal input from the RF demodulator
54
NC
O
Not used
55
T_SENSE
O
Not used
25
SA-TSLF1
Pin No.
Pin Name
I/O
Description
56
VCC
—
Power supply terminal (+3.3V)
57
MAIN_OFF
O
Power off control signal output to the power control “H”: power off
58
V_CONT
O
Voltage control PWM signal output to the shunt regulator
59
DAMP_LATCH
O
Latch control signal output to the stream processor
60
DAMP_SHIFT
O
Shift clock signal output to the stream processor
61
DAMP_SCDT
O
Serial data output to the stream processor
62
SI2
I
Serial data input terminal
63
INT24
O
Not used
64
NC
O
Not used
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