Sony DAV-LF1 / HCD-LF1 Service Manual ▷ View online
69
HCD-LF1
Pin No.
Pin Name
I/O
Description
85
GND25
—
Ground terminal
86
MDQM2
O
Write mask signal output to the SD-RAM
87
VDD25
—
Power supply terminal (+3.3V)
88 to 95
MD20 to MD27
I/O
Two-way data bus with the SD-RAM
96
GND25
—
Ground terminal
97
MDQM3
O
Write mask signal output to the SD-RAM
98
VDD25
—
Power supply terminal (+3.3V)
99 to 102
MD28 to MD31
I/O
Two-way data bus with the SD-RAM
103
GND25
—
Ground terminal
104
VDD25
—
Power supply terminal (+3.3V)
105
VCLK
O
Not used
106
XCK_I/O_SEL
O
Not used
107
VS
O
Wide control signal output terminal
108
I/P SW
O
Interlace/progressive selection signal output terminal Not used
109
CDSEL
O
Digital out signal selection signal output terminal Not used
110
MREQ
O
Audio muting on/off request signal output to the system controller “H”: muting on
111
VDDP
—
Power supply terminal (+3.3V)
112
GNDP
—
Ground terminal
113
MDI
O
Serial data output terminal
114
MC
O
Serial data transfer clock signal output terminal
115
ML
O
Serial data latch pulse signal output terminal
116
HIRQ2
I
Busy signal input from the EEPROM
117
VDAC_4B
—
Ground terminal
118
VDAC_VDD4
—
Power supply terminal (+3.3V)
119
VDAC_4
O
Component video signal output to the video amplifier
120
VDAC_3B
—
Ground terminal
121
VDAC_VDD3
—
Power supply terminal (+3.3V)
122
VDAC_3
O
Component video signal output to the video amplifier
123
VDAC_2B
—
Ground terminal
124
VDAC_VDD2
—
Power supply terminal (+3.3V)
125
VDAC_2
O
Component video signal output to the video amplifier
126
VDAC_1B
—
Ground terminal
127
VDAC_VDD1
—
Power supply terminal (+3.3V)
128
VDAC_1
O
Component video signal output to the video amplifier
129
VDAC_0B
—
Ground terminal
130
VDAC_VDD0
—
Power supply terminal (+3.3V)
131
VDAC_0
O
Component video signal output to the video amplifier
132
VDAC_DVSS
—
Ground terminal
133
VDAC_DVDD
—
Power supply terminal (+3.3V)
134
VDAC_REFVDD
—
Power supply terminal (+3.3V)
135
VDAC_REF
I
Reference voltage input terminal
136
VDAC_REFVSS
—
Ground terminal
137
XVSS
—
Ground terminal
138
XOUT
O
Clock signal output terminal Not used
139
XIN
I
System clock signal (27 MHz) input from the clock generator
140
XVDD
—
Power supply terminal (+3.3V)
141
AVSS2
—
Ground terminal
70
HCD-LF1
Pin No.
Pin Name
I/O
Description
142
AVDD2
—
Power supply terminal (+3.3V)
143
AVDD1
—
Power supply terminal (+3.3V)
144
AVSS1
—
Ground terminal
145
VDD
—
Power supply terminal (+1.8V)
146
GND
—
Ground terminal
147
XCK
O
Audio system clock output to the A/D converter and digital audio processor
148
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital audio processor
149
BCK
O
Bit clock signal (2.8224 MHz) output to the digital audio processor
150
DATA0 (DM)
O
Audio data (for down mix) output terminal
151
DATA1 (FLR)
O
Audio data (for front) output to the digital audio processor
152
VDDP
—
Power supply terminal (+3.3V)
153
GNDP
—
Ground terminal
154
DATA2 (SLR)
O
Audio data (for surround (rear)) output to the digital audio processor
155
DATA3 (CSW)
O
Audio data (for center and sub woofer) output to the digital audio processor
156
IEC958
O
S/PDIF signal output terminal Not used
157
DAI_DATA
I
Data input terminal Not used
158
DAI_BCK
I
Bit clock signal (2.8224 MHz) input terminal Not used
159
DAI_LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
160
I2C_CL
I/O
Two-way I2C clock bus with the system controller and mechanism controller
161
I2C_DA
I/O
Two-way I2C data bus with the system controller and mechanism controller
162
CS (ZIVA_E2P)
O
Chip select signal output to the EEPROM
163
RXD1
I
Serial data input terminal for check jig
164
TXD1
O
Serial data output terminal for check jig
165
WRITE_CTRL
O
Write control signal output to the EEPROM
(ZIVA_E2P)
166
GNDP
—
Ground terminal
167
VDDP
—
Power supply terminal (+3.3V)
168 to 171 SDDATA7 to SDDATA4
I
Stream data signal input from the DVD decoder
172
GND
—
Ground terminal
173
VDD
—
Power supply terminal (+1.8V)
174 to 177 SDDATA3 to SDDATA0
I
Stream data signal input from the DVD decoder
178
SDREQ
O
Serial data request signal output to the DVD decoder
179
SDEN
I
Serial data enable signal input from the DVD decoder
180
GNDP
—
Ground terminal
181
VDDP
—
Power supply terminal
182
SDERROR
I
Serial data error signal input from the DVD decoder
183
SDCLK
I
Serial data transfer clock signal input from the DVD decoder
184
HIRQ1
I
Interrupt request signal input from the mechanism controller
185
DRVCLK
I
Serial data transfer clock signal input from the mechanism controller
186
DRVTX
I
Serial data input from the EEPROM and mechanism controller
187
DRVRX
O
Serial data output to the EEPROM and mechanism controller
188
DRVRDY
I
Ready signal input from the mechanism controller
189
VNW
—
Power supply terminal (+5V)
190
ALE
O
Latch enable signal output to the address latch
191
RST_SPC
O
Reset signal output to the mechanism controller “L”: reset
192
INT/EXT
O
Internal/external selection signal output terminal
193, 194
HCS2, HCS1
O
Chip select signal output terminal Not used
71
HCD-LF1
Pin No.
Pin Name
I/O
Description
195
HCS0
O
Chip select signal output to the programmable ROM
196
VDDP
—
Power supply terminal (+3.3V)
197
TRST
I
Reset signal input terminal (for JTAG)
198
TDO
O
Data output terminal (for JTAG)
199
TDI
I
Data input terminal (for JTAG) Not used
200
TMS
I
Mode selection signal input terminal (for JTAG)
201
TCK
I
Clock signal input terminal (for JTAG)
202
RESET
I
System reset signal input from the system controller “L”: reset
203
BUS CLK
O
Not used
204
GND
—
Ground terminal
205
VDD
—
Power supply terminal (+1.8V)
206
HA3
O
Address signal output to the programmable ROM
207
HA2
O
Address signal output to the programmable ROM and address latch
208
GNDP
—
Ground terminal
72
HCD-LF1
• DMB07 BOARD IC701 TMC57929PGF-RDP (DVD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the mechanism controller
3
VSS
—
Ground terminal
4
D7
I/O
Two-way data bus with the mechanism controller
5
A0
I
Address signal input from the mechanism controller
6
VDD
—
Power supply terminal (+3.3V)
7
A1
I
Address signal input from the mechanism controller
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the mechanism controller
15
VSS
—
Ground terminal
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the mechanism controller
18
XWR
I
Write strobe signal input from the mechanism controller
19
XCS
I
Chip select signal input from the mechanism controller
20, 21
XINT0, XINT1
O
Interrupt signal output to the mechanism controller
22
VDD
—
Power supply terminal (+3.3V)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DVD system processor and DSD decoder
25
VSS
—
Ground terminal
26
SDEF
O
Error flag signal output to the DVD system processor and DSD decoder
27
HDB6
O
Stream data signal output to the DVD system processor and DSD decoder
28
VDDS
—
Power supply terminal (+5V)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DVD system processor and DSD decoder
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DVD system processor and DSD decoder
33
VSS
—
Ground terminal
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DVD system processor and DSD decoder
36
VDD
—
Power supply terminal (+3.3V)
37
HDBC
O
Not used
38
VDDS
—
Power supply terminal (+5V)
39
HDB2
O
Stream data signal output to the DVD system processor and DSD decoder
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DVD system processor and DSD decoder
42
VSS
—
Ground terminal
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DVD system processor and DSD decoder
45
HDBF
O
Not used
46
HDRQ
O
Serial data effect flag signal output to the DVD system processor and DSD
decoder
47
VDDS
—
Power supply terminal (+5V)
48
XDCK
O
Serial data transfer clock signal output to the DVD system processor and DSD
decoder
49
XSHD
O
Header flag signal output to the DSD decoder
50
VDD
—
Power supply terminal (+3.3V)
51
REDY
O
Not used
52
VSS
—
Ground terminal
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