Sony DAV-IS50 / SA-WSIS50 Service Manual ▷ View online
33
SA-WSIS50
• IC Pin Function Descriptions
IC611 R5F3640MDFA (System Controller) DSP board
IC611 R5F3640MDFA (System Controller) DSP board
Pin No.
Pin Name
I/O
Pin Description
1
DAMP_SCDT/DIR_DIN
O
Serial data output to the digital audio interface receiver and stream processor
2
DAMP_SHIFT/DIR_CLK
O
Shift clock signal output to the digital audio interface receiver and stream processor
3
DSP_INT
I
Interrupt signal input from the DSP
4
—
—
Not Used
5
DSP_MOSI
O
Serial data output to the DSP
6
DSP_MISO
I
Serial data input from the DSP
7
DSP_SPICLK
O
Serial data transfer clock signal output to the DSP
8
BYTE
I
External data bus width selection signal input terminal Fixed at “L” in this set
9
CNVss
I
Processor mode switch input terminal (for test)
10,11
—
—
Not Used
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
13
Xout
O
Main system clock output terminal (10MHz)
14
Vss
—
Ground Terminal
15
Xin
I
Main system clock input terminal (10MHz)
16
Vcc1
—
Power Supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
DIR_ZERO
I
Audio serial data input from the digital audio interface receiver
19
DIR_CSFLAG
I
CSFLAG data input from the digital audio interface receiver
20
AC_CUT
I
AC cut detection signal input terminal “L” : AC cut on
21 to 26
—
—
Not Used
27
DIR_ERROR
I
Error signal input from the digital audio interface receiver
28
P_CONT_FL
O
Power on/off control signal output terminal “H”: power on
29
12C_CLK
I/O
Two way 12C clock bus terminal (Not used)
30
12C_DATA
I/O
Two way 12C data bus terminal (Not used)
31
SYS_TXD
O
Serial data output from the SYSTEM CONTROL connector (HCD-IS50)
32
SYS_RXD
I
Serial data input to the SYSTEM CONTROL connector (HCD-IS50)
33
SYS_CLK
I
Serial data transfer clock signal input to the SYSTEM CONTROL connector (HCD-IS50)
34
SYS_BUSY
O
Busy signal output from the SYSTEM CONTROL connector (HCD-IS50)
35
EEPROM_SDA
I/O
Serial data input/output with the EEPROM
36
EEPROM_SCL
I/O
Serial clock signal input/output with the EEPROM
37, 38
—
—
Not Used
39
P_CONT2
O
Power on/off control signal output terminal “H” : power on
40
P_CONT1
O
Power on/off control signal output terminal “H” : power on
41
EPM
I
Not Used
42, 43
—
—
Not Used
44
P_CONT_SAIR
O
Power on/off control signal output terminal for SAIR
45
P_CONT_DSP
O
Power on/off control signal output terminal for the DSP “H”: power on
46
CE
—
Not Used
47
DAMP_INIT
O
Reset signal output to the stream processor “L” : reset
48
SOFT_MUTE
O
Soft muting on/off control signal output to the stream processor “L” : muting on
49, 50
DAMP_LATCH1,
DAMP_LATCH3
O
Serial data latch pulse signal output to the stream processor
51
DRIVE_RST (EN)
O
Reset signal output to the digital power amplifi er “L” : reset
52
—
—
Not Used
53, 54
OVERFLOW1,
OVERLFOW2
I
Over fl ow status input from the stream processor
55
DSP_RESET
O
Reset signal output to DSP “L” : reset
56
DSP_SPIDS
O
Device selection signal output to the DSP
57
DIR_RST
O
Reset signal output to the digital audio interface receiver “L” : reset
58
DIR_HCE
O
Chip enable signal output to the digital interface receiver
59
OVERFLOW3
I
Over fl ow status input from the stream processor
60
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
61
—
—
Not Used
62
Vcc2
—
Power Supply terminal (+3.3V)
34
SA-WSIS50
Pin No.
Pin Name
I/O
Pin Description
63
—
—
Not Used
64
Vss
—
Ground Terminal
65
DC_DET
I
Over load detection signal input terminal
66
DAMP_LATCH2,
DAMP_LATCH4
O
Serial data latch pulse signal output to the stream processor
68
S-AIR_GPIO2
O
Interrupt signal input from S-AIR
69 to 72
—
—
Not Used
73
CABLE_DETECT
I
Connect detection signal input from the SYSTEM CONTROL connector (HCD-IS50)
74
SYS_WAKE UP
I
System wake up signal input from the SYSTEM CONTROL connector (HCD-IS50)
75
DRIVE_OCP (DIAG)
I
Shut down state input from the digital power amplifi er “L” : shut down
76
S-AIR_ADC_SEL
O
Analog digital converter selection terminal for S-AIR
77
S-AIR_12C_SDA
O
12C data signal output terminal from S-Air
78
S-AIR_12C_SCL
O
12C clock signal output terminal from S-Air
79
S-AIR_SRC_MUTE
O
Muting port signal output terminal from S-AIR
80
S-AIR_RST
O
Reset signal output to S-AIR
81
S-AIR-DET
I
Connect detection signal input from S-AIR
82 to 86
TEST1 TO TEST 5
—
Not Used
87
SYS_RESET
O
Reset signal output terminal to SYSTEM CONTROL connector
88 to 90
—
—
Not Used
91
DEVICE
O
Device selection signal output terminal
92
DEST
I
Setting terminal for the destination
93
MODEL
I
Setting terminal for the model
94 to 95
—
—
Not Used
96
AVss
—
Ground Terminal
97
—
—
Not Used
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVcc
—
Power Supply terminal (+3.3V)
100
DIR_HDOUT
I
Read data input from the digital audio interface receiver
35
SA-WSIS50
DSP BOARD IC821 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Pin Description
1
VDDINT
—
Power supply terminal (+1.2V) (for core)
2
CLKCFG0
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “L” in this set
Fixed at “L” in this set
3
CLKCFG1
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “H” in this set
Fixed at “H” in this set
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode selection signal input terminal Fixed at “H” in this set
6
GND
—
Ground terminal
7
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
8
GND
—
Ground terminal
9
VDDINT
—
Power supply terminal (+1.2V) (for core)
10
GND
—
Ground terminal
11
VDDINT
—
Power supply terminal (+1.2V) (for core)
12
GND
—
Ground terminal
13
VDDINT
—
Power supply terminal (+1.2V) (for core)
14
GND
—
Ground terminal
15
INT_REQ
O
Interrupt signal output to the system controller
16
DIR_ERR
I
PLL lock error signal and data error fl ag input from the digital audio interface receiver
17
AD7
I/O
Two-way address and data bus terminal Not used
18
GND
—
Ground terminal
19
VDDINT
—
Power supply terminal (+1.2V) (for core)
20
GND
—
Ground terminal
21
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
22
GND
—
Ground terminal
23
VDDINT
—
Power supply terminal (+1.2V) (for core)
24 to 26
AD6 to AD4
I/O
Two-way address and data bus terminal Not used
27
VDDINT
—
Power supply terminal (+1.2V) (for core)
28
GND
—
Ground terminal
29, 30
AD3, AD2
I/O
Two-way address and data bus terminal Not used
31
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
32
GND
—
Ground terminal
33, 34
AD1, AD0
I/O
Two-way address and data bus terminal Not used
35
WR*
O
Write enable signal output terminal Not used
36, 37
VDDINT
—
Power supply terminal (+1.2V) (for core)
38
GND
—
Ground terminal
39
RD*
O
Read enable signal output terminal Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way address and data bus terminal Not used
44
GND
—
Ground terminal
45
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
46
AD12
I/O
Two-way address and data bus terminal Not used
47
VDDINT
—
Power supply terminal (+1.2V) (for core)
48
GND
—
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way address and data bus terminal Not used
53
A16
—
Not used
54
VDDINT
—
Power supply terminal (+1.2V) (for core)
55
GND
—
Ground terminal
56, 57
A17, A18
—
Not used
58
GND
—
Ground terminal
59
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
60
VDDINT
—
Power supply terminal (+1.2V) (for core)
61
GND
—
Ground terminal
62
PF_CE
—
Not used
63
SPI_MAS
—
Not used
64, 65
DPSOA, DPSOB
O
Audio serial data output to the stream processor
66
VDDINT
—
Power supply terminal (+1.2V) (for core)
36
SA-WSIS50
Pin No.
Pin Name
I/O
Pin Description
67
GND
—
Ground terminal
68
VDDINT
—
Power supply terminal (+1.2V) (for core)
69
GND
—
Ground terminal
70, 71
DPSOC, DPSOD
O
Audio serial data output to the stream processor
72
VDDINT
—
Power supply terminal (+1.2V) (for core)
73
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
74
GND
—
Ground terminal
75
VDDINT
—
Power supply terminal (+1.2V) (for core)
76
GND
—
Ground terminal
77
DPSOE
O
Audio serial data output terminal
78, 79
DPSIA, DPSIB
I
Audio serial data input from the digital audio interface receiver
80, 81
DPSIC, DPSID
I
Audio serial data input terminal Not used
82
DPSIE
I
Audio serial data input from the digital audio interface receiver
83
VDDINT
—
Power supply terminal (+1.2V) (for core)
84, 85
GND
—
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the stream processor
87
DPDVBCK
O
Bit clock signal output to the stream processor
88
DPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver
89
DPBCK
I
Bit clock signal input from the digital audio interface receiver
90
VDDINT
—
Power supply terminal (+1.2V) (for core)
91, 92
GND
—
Ground terminal
93
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
94
DPFSCK
I
Audio clock signal input from the digital audio interface receiver
95
GND
—
Ground terminal
96
VDDINT
—
Power supply terminal (+1.2V) (for core)
97
NONAUDIO*
I
PCM audio data input from the digital audio interface receiver
98
SF_CE*
—
Not used
99
VDDINT
—
Power supply terminal (+1.2V) (for core)
100
GND
—
Ground terminal
101
VDDINT
—
Power supply terminal (+1.2V) (for core)
102
GND
—
Ground terminal
103
VDDINT
—
Power supply terminal (+1.2V) (for core)
104
GND
—
Ground terminal
105
VDDINT
—
Power supply terminal (+1.2V) (for core)
106
GND
—
Ground terminal
107, 108
VDDINT
—
Power supply terminal (+1.2V) (for core)
109
GND
—
Ground terminal
110
VDDINT
—
Power supply terminal (+1.2V) (for core)
111
GND
—
Ground terminal
112
VDDINT
—
Power supply terminal (+1.2V) (for core)
113
GND
—
Ground terminal
114
VDDINT
—
Power supply terminal (+1.2V) (for core)
115
GND
—
Ground terminal
116
VDDEXT
—
Power supply terminal (+3.3V) (for I/0)
117
GND
—
Ground terminal
118
VDDINT
—
Power supply terminal (+1.2V) (for core)
119
GND
—
Ground terminal
120
VDDINT
—
Power supply terminal (+1.2V) (for core)
121
RESET*
I
Reset signal input from the system controller “L”: reset
122
SPIDS*
I
Device selection signal input from the system controller
123
GND
—
Ground terminal
124
VDDINT
—
Power supply terminal (+1.2V) (for core)
125
SPICLK
I
Serial data transfer clock signal input from the system controller
126
MISO
O
Serial data output to the system controller
127
MOSI
I
Serial data input from the system controller
128
GND
—
Ground terminal
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