Sony DAV-IS10 / SA-WSIS10 / SS-IS10 Service Manual ▷ View online
33
SA-WSIS10/SS-IS10
•
IC Pin Function Description
DSP BOARD IC611 M30626MHP-A72FPU0 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT/
DIR_DIN
O
Serial data output to the digital audio interface receiver and stream processor
2
DAMP_SHIFT/
DIR_CLK
O
Shift clock signal output to the digital audio interface receiver and stream processor
3
DSP_INT
I
Interrupt signal input from the DSP
4
-
-
Not used
5
DSP_MOSI
O
Serial data output to the DSP
6
DSP_MISO
I
Serial data input from the DSP
7
DSP_SPICLK
O
Serial data transfer clock signal output to the DSP
8
BYTE
I
External data bus width selection signal input terminal Fixed at "L" in this set
9
CNVss
I
Processor mode switch input terminal (for test)
10, 11
-
-
Not used
12
RESET
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
13
Xout
O
Main system clock output terminal (10 MHz)
14
Vss
-
Ground terminal
15
Xin
I
Main system clock input terminal (10 MHz)
16
Vcc1
-
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at "H" in this set
18
DIR_ZERO
I
Audio serial data input from the digital audio interface receiver
19
DIR_CSFLAG
I
CSFLAG data input from the digital audio interface receiver
20
AC_CUT
I
AC cut detection signal input terminal "L": AC cut on
21 to 26
-
-
Not used
27
DIR_ERROR
I
Error signal input from the digital audio interface receiver
28
P_CONT_FL
O
Power on/off control signal output terminal "H": power on
29
IIC_CLK
I/O
Two-way I2C clock bus terminal Not used
30
IIC_DATA
I/O
Two-way I2C data bus terminal Not used
31
SYS_TXD
O
Serial data output to the SYSTEM CONTROL connector (HCD-IS10)
32
SYS_RXD
I
Serial data input from the SYSTEM CONTROL connector (HCD-IS10)
33
SYS_CLK
I
Serial data transfer clock signal input from the SYSTEM CONTROL connector (HCD-IS10)
34
SYS_BUSY
O
Busy signal output to the SYSTEM CONTROL connector (HCD-IS10)
35 to 38
-
-
Not used
39, 40
P_CONT2,
P_CONT1
O
Power on/off control signal output terminal "H": power on
41
EPM
I
Not used
42 to 44
-
-
Not used
45
P_CONT_DSP
O
Power on/off control signal output terminal for the DSP "H": power on
46
CE
I
Chip enable signal input terminal Not used
47
DAMP_INIT
O
Reset signal output to the stream processor "L": reset
48
DAMP_SOFT_
MUTE
O
Soft muting on/off control signal output to the stream processor "L": muting on
49, 50
DAMP_LATCH1,
DAMP_LATCH3
O
Serial data latch pulse signal output to the stream processor
51
DRIVE_RST (EN)
O
Reset signal output to the digital power amplifier "L": reset
52
-
-
Not used
53, 54
OVERFLOW1,
OVERFLOW2
I
Over flow status input from the stream processor
34
SA-WSIS10/SS-IS10
Pin No.
Pin Name
I/O
Description
55
DSP_RESET
O
Reset signal output to the DSP "L": reset
56
DSP_SPIDS
O
Device selection signal output to the DSP
57
DIR_RST
O
Reset signal output to the digital audio interface receiver "L": reset
58
DIR_HCE
O
Chip enable signal output to the digital audio interface receiver
59
OVERFLOW3
I
Over flow status input from the stream processor
60
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
61
-
-
Not used
62
Vcc2
-
Power supply terminal (+3.3V)
63
-
-
Not used
64
Vss
-
Ground terminal
65
DC_DET
I
Over load detection signal input terminal
66, 67
DAMP_LATCH2,
DAMP_LATCH4
O
Serial data latch pulse signal output to the stream processor
68 to 72
-
-
Not used
73
CABLE DETECT
I
Connect detection signal input from the SYSTEM CONTROL connector (HCD-IS10)
74
SYS_WAKEUP
I
System wake up signal input from the SYSTEM CONTROL connector (HCD-IS10)
75
DRIVE_OCP
(DIAG)
I
Shut down state input from the digital power amplifier "L": shut down
76 to 86
-
-
Not used
87
SYS_RESET
O
System reset signal output to the SYSTEM CONTROL connector (HCD-IS10)
88 to 90
-
-
Not used
91
DEVICE
O
Device selection signal output terminal Not used
92
DEST
I
Setting terminal for the destination
93
MODEL
I
Setting terminal for the model
94, 95
-
-
Not used
96
AVss
-
Ground terminal
97
-
-
Not used
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVcc
-
Power supply terminal (+3.3V)
100
DIR_HDOUT
I
Read data input from the digital audio interface receiver
35
SA-WSIS10/SS-IS10
DSP BOARD IC821 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V) (for core)
2
CLKCFG0
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at "L" in this set
Fixed at "L" in this set
3
CLKCFG1
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at "H" in this set
Fixed at "H" in this set
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode selection signal input terminal Fixed at "H" in this set
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V) (for core)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V) (for core)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V) (for core)
14
GND
-
Ground terminal
15
INT_REQ
O
Interrupt signal output to the system controller
16
DIR_ERR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
17
AD7
I/O
Two-way address and data bus terminal Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V) (for core)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V) (for core)
24 to 26
AD6 to AD4
I/O
Two-way address and data bus terminal Not used
27
VDDINT
-
Power supply terminal (+1.2V) (for core)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way address and data bus terminal Not used
31
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way address and data bus terminal Not used
35
WR*
O
Write enable signal output terminal Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V) (for core)
38
GND
-
Ground terminal
39
RD*
O
Read enable signal output terminal Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way address and data bus terminal Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
46
AD12
I/O
Two-way address and data bus terminal Not used
47
VDDINT
-
Power supply terminal (+1.2V) (for core)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way address and data bus terminal Not used
53
A16
-
Not used
54
VDDINT
-
Power supply terminal (+1.2V) (for core)
55
GND
-
Ground terminal
36
SA-WSIS10/SS-IS10
Pin No.
Pin Name
I/O
Description
56, 57
A17, A18
-
Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
60
VDDINT
-
Power supply terminal (+1.2V) (for core)
61
GND
-
Ground terminal
62
PF_CE
-
Not used
63
SPI_MAS
-
Not used
64, 65
DPSOA, DPSOB
O
Audio serial data output to the stream processor
66
VDDINT
-
Power supply terminal (+1.2V) (for core)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V) (for core)
69
GND
-
Ground terminal
70, 71
DPSOC, DPSOD
O
Audio serial data output to the stream processor
72
VDDINT
-
Power supply terminal (+1.2V) (for core)
73
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V) (for core)
76
GND
-
Ground terminal
77
DPSOE
O
Audio serial data output terminal Not used
78, 79
DPSIA, DPSIB
I
Audio serial data input from the digital audio interface receiver
80, 81
DPSIC, DPSID
I
Audio serial data input terminal Not used
82
DPSIE
I
Audio serial data input from the digital audio interface receiver
83
VDDINT
-
Power supply terminal (+1.2V) (for core)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the stream processor
87
DPDVBCK
O
Bit clock signal output to the stream processor
88
DPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver
89
DPBCK
I
Bit clock signal input from the digital audio interface receiver
90
VDDINT
-
Power supply terminal (+1.2V) (for core)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V) (for I/0)
94
DPFSCK
I
Audio clock signal input from the digital audio interface receiver
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V) (for core)
97
NONAUDIO*
I
PCM audio data input from the digital audio interface receiver
98
SF_CE*
-
Not used
99
VDDINT
-
Power supply terminal (+1.2V) (for core)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V) (for core)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V) (for core)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V) (for core)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V) (for core)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V) (for core)
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