Sony DAV-DZ260 / DAV-DZ270 / HCD-DZ260 / HCD-DZ270 / HCD-HDZ278 Service Manual ▷ View online
HCD-DZ260/DZ270/HDZ278
65
Pin No.
Pin Name
I/O
Description
53
LIMITSW
I
LIMIT SW signal input
54
MSW
O
DVD/CD PD –VR select signal output
55
DVDD18
—
Power supply (+1.8V)
56 to 62
HA2 to HA8
O
Flash ROM address bus A2 to A8 output
63, 64
HA18, HA19
O
Flash ROM address bus A18, A19 output
65
DVDD3
—
Power supply (+3.3V)
66
XWR
O
Flash ROM write signal output
67 to 74
HA16 to HA9
O
Flash ROM address bus A16 to A9 output
75
HA20
Flash ROM address bus A20 output
76
XROMCS
O
Flash ROM chip select signal output
77
HA1
O
Flash ROM address bus A1 output
78
XRD
O
Flash ROM read signal output
79, 80
HD0, HD1
I/O
Flash ROM data bus D0, D1 input/output
81
DVSS
—
Ground terminal
82 to 86
HD2 to HD6
I/O
Flash ROM data bus D2 to D6 input/output
87
HA21
I/O
Flash ROM data bus D21 input/output
88
RESERVED
—
Not used (Open)
89
HD7
I/O
Flash ROM data bus D7 input/output
90
DVSS
—
Ground terminal
91, 92
HA17, HA0
O
Flash ROM address bus A17, A0 output
93
DVDD18
O
Flash ROM data bus D18 input/output
94
FWR
O
Loading motor control (FWR) signal output
95
REV
O
Loading motor control (REV) signal output
96
DVDD3
—
Power supply (+3.3V)
97
IFSDO
O
CPU I/F serial data output
98
IFCK
O
CPU I/F serial clock output
99
xIFCS
O
CPU I/F chip select output
100
IFSDI
I
CPU I/F serial data input
101
SCL
O
EEPROM serial clock output
102
SDA
I/O
EEPROM serial data input/output
103
CKSW
I
Chuck/Tray detect switch signal input
104
OCSW
I
Chuck/Tray detect switch signal input
105
RXD
I
RXD signal input from Jig
106
TXD
O
TXD signal output to Jig
107
ICE
O
Not used (Open)
108
xSYSRST
I
System reset signal input
109
RESERVED
I
Not used (Open)
110
xIFBSY
I
Busy signal input from CPU I/F
111
DQM0
O
SDRAM lower byte mask signal output
112
EEWP
I
EEPROM ready/Busy wake up signal input
113 to 117
RD7 to 3
I/O
SDROM data bus D7 to D3 input/output
118
DVDD3
—
Power supply (+3.3V)
119 to 121
RD2 to RD0
I/O
SDROM data bus D2 to D0 input/output
122 to 129
RD15 to RD8
I/O
SDROM data bus D15 to D8 input/output
130
TSD_M
I
TSD signal input
131
DVDD3
—
Power supply (+3.3V)
132
DQM1
O
SDRAM lower byte mask signal output
133
_RWE
O
SDRAM write enable signal output
134
_CAS
O
SDRAM column address strobe signal output
135
_RAS
O
SDRAM row address strobe signal output
136
_RCS
O
SDRAM chip select signal output
137, 138
BA0, BA1
O
SDRAM bank address 0, 1 output
139
RA10
O
SDRAM address bus A10 output
140, 141
RA0, RA1
O
SDRAM address bus A0, A1 output
142
DVDD18
—
Power supply (+1.8V)
143, 144
RA2, RA3
O
SDRAM address bus A0, A3 output
HCD-DZ260/DZ270/HDZ278
66
Pin No.
Pin Name
I/O
Description
145
DVDD3
—
Power supply (+3.3V)
146
DRCLK
O
SDRAM clock output
147
CKE
O
SDRAM clock enable signal output
148
DVSS
—
Ground terminal
149
RA11
O
SDRAM address bus A11 output
150 to 155
RA9 to RA4
O
SDRAM address bus A9 to A4 output
156
DVDD3
—
Power supply (+3.3V)
157
MUTE123
O
Mute signal output for Focus/Tracking/Sledding
158
MUTE
O
Mute signal output for Spindle motor
159
DDC_DA
I/O
HDMI DDC line data input/output
160
DVDD18
—
Power supply (+1.8V)
161
DDC_CLK
I/O
HDMI DDC line clock input/output
162
HIPLG
I
HDMI HPD signal input
163
AGND3
—
Ground
164
EXT_RES
I
Ext. resistor connected terminal
165, 166
AVDD3
—
Power supply (+3.3V)
167
EXT_CAP
I
Ext. capacitor connected terminal
168, 169
AGND3, AGND18
—
Ground
170
TXCN
O
HDMI TXD-clock output
171
TXCP
O
HDMI TXD-clock output
172
AVDD18
—
Power supply (+1.8V)
173
TX0N
O
HDMI TXD-0 output
174
TX0P
O
HDMI TXD-0 output
175
AGND18
—
Power supply (+1.8V)
176
TX1N
O
HDMI TXD-1 output
177
TX1P
O
HDMI TXD-1 output
178
AVD18
—
Power supply (+1.8V)
179
TX2N
O
HDMI TXD-2 output
180
TX2P
O
HDMI TXD-2 output
181
AGND18
—
Power supply (+1.8V)
182
R/Cr/Pr
O
Video chroma R/Cr/Pr signal output
183
B/Cb/Pb
O
Video chroma B/Cb/Pb signal output
184
DACVSSA
—
Ground
185
Y/G
O
Video Y/chroma G signal output
186
DACVDDA
—
Power supply (+3.3V)
187
CVBS
O
Video Composite signal output
188
DACVSSB
—
Ground
189
C
O
Video chroma signal output
190
DACVDDB
—
Power supply (+3.3V)
191
Y
O
Video Y signal output
192
DACVSSC
—
Ground
193
FS
I
Full Scale Adjustment setting terminal
194
VREF
I
Reference Voltage input terminal
195
DACVDDC
—
Power supply (+3.3V)
196
VBUS_OE
O
VBUS power control signal output
197
VBUS_OC
I
VBUS detect signal input
198
SCORE/DIR_XSTATE
I
DIR status signal input
199
SPMCK
I
DIR MCK clock input
200
SPBCK
I
DIR BCK clock input
201
SPLRCK
I
DIR LRCK clock input
202
ADIN (SPDATA)
I
Audio digital data input
203
ACLK
O
A/D converter and DAMP clock output
204
ABCK
O
A/D converter and DAMP BCK clock output
205
ALRCK
O
A/D converter and DAMP LRCK clock output
206
MC_DATA (ADIN)
I
A/D converter data input
207
DVDD3
—
Power supply (+3.3V)
HCD-DZ260/DZ270/HDZ278
67
Pin No.
Pin Name
I/O
Description
208
MIC
O
Not used (Fixed to Ground)
209
WIDE
O
WIDE select signal output
210
RGB_SEL/DSEL
O
Video output select signal output
211
TRG_SW
I
Not used
212
DVDD18
—
Power supply (+3.3V)
213
KMOD
O
Not used (Open)
214
XVOICE/DIR_CSFLAG
O
Not used (Open)
215
SPDIF
O
Not used (Open)
216
APLLVDD3
—
Power supply (+3.3V)
217
APLLCAP
—
Ext capacitor connected terminal
218
APLLVSS
—
Ground
219
ADACVSS2
—
Ground
220
ADACVSS1
—
Ground
221
DIR_CE
O
DIR I/F chip select signal output
222
ASDATA3
O
Audio digital signal output to D-AMP (Not used in this set)
223
ASDATA2
O
Audio digital signal output to D-AMP
224
AVCM
—
Ext capacitor connected terminal
225
ASDATA1
O
Audio digital signal output to D-AMP
226
ASDATA0
O
Audio digital signal output to D-AMP
227
DIR_CL
O
DIR I/F clock output
228
ADACVDD1
—
Power supply (+3.3V)
229
ADACVDD2
—
Power supply (+3.3V)
230
Rt/DIR_DI
O
DIR I/F data output
231
Lt/DIR_DO
I
DIR I/F data input
232
ADACSS3
—
Ground
233
ADACVDD3
—
Power supply (+3.3V)
234
SADCVDD18
—
Power supply (+1.8V)
235
SADCVSS18
—
Ground
236
FGND18
—
Ground
237
RFVDD18
—
Power supply (+1.8V)
238
XTALO
O
Crystal output for main clock (27MHz)
239
XTALI
I
Crystal input for main clock (27MHz)
240
JITFO
O
The output terminal of RF jitter meter
241
JITFN
I
The input terminal of RF jitter meter
242
PLLVSS
—
Ground
243
PLLVDD3
—
Power supply (+3.3V)
244
LPFON
O
The negative output of loop fi lter amplifi er
245
LPFIP
I
The positive input terminal of loop fi lter amplifi er
246
LPFIN
I
The negative input terminal of loop fi lter amplifi er
247
LPFOP
O
The positive output of loop fi lter amplifi er
248
ADCVDD3
—
Power supply (+3.3V)
249
ADCVSS
—
Ground
250
RFVDD3
—
Power supply (+3.3V)
251
RFRPDC
O
RF ripple detect output
252
RFRPAC
I
RF ripple detect input (through AC-coupling)
253
HRFZC
I
High frequency RF ripple zero crossing
254
CRTPLP
O
Defect level fi lter capacitor connected terminal
255
RFGND18
—
Power supply (+3.3V)
256
OSP
O
RF offset cancellation capacitor connecting
HCD-DZ260/DZ270/HDZ278
68
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT/DIR_DIN
O
D-AMP processor and DIR data output
2
DAMP_SHIFT/DIR_CLK
O
D-AMP processor and DIR clock output
3
CEC_RX_IN
I
CEC data input
4
SIRCS_IN
I
Sircs input
5
DSP_MOSI/ASEL4
O
Audio input select signal output. (Not used in this set)
6
DSP_MISO/ASEL5
O
Audio input select signal output. (Not used in this set)
7
DSP_SPICLK
O
Not used (Open)
8
BYTE
I
External data bus input. (Connected to ground)
9
CNVSS
I
Change processor mode input (L: Single chip mode)
10, 11
EN_A, EN_B
I
Volume control pulse input for ENCODER
12
RESET
I
System reset signal input
13
XOUT
O
Crystal output for main clock (5MHz)
14
VSS
—
Ground
15
XIN
I
Crystal input for main clock (5MHz)
16
VCC
—
Power supply (BUP+3.3V)
17
NMI
I
Not used (Fixed to “H” (BUP+3.3V))
18
DIR_ZERO INT2
O
Not used (Open)
19
DIRCSFLAG INT3
/A.CAL_OUT_LEVEL
I
Out level detect for auto calibration input
20
AC_CUT INT0
I
AC-CUT detect signal input
21
FL_CLK/LED_CLK
O
FL and LED driver clock output
22
CEC_TX_OUT
O
CEC data output
23
FL_CS/STB
O
FL and LED driver chip select signal output
24
FL_D_OUT/LED_DATA
O
FL and LED driver data output
25
DIVER_RST_CS/
S-AIR_SRC_MUTE
O
Not used (Open)
26
MIC_GAIN
O
MIC gain control signal output
27
CDM_OPEN_SW/
XM_SEL
I
CDM open switch signal input
28
DC_CONT
O
A.CAL MIC DC control signal output
29
DMP_RX_IN
I
DMPORT data input
30
DMP_TX_OUT
O
DMPORT data output
31
DVD_SID
O
Serial data output to CDX9917R/CDX9927R
32
DVD_SOD
I
Serial data input from CDX9917R/CDX9927R
33
DVD_SCO
I
Serial clock input from CDX9917R/CDX9927R
34
DVD_XIFBUSY
O
RTS signal output to CDX9917R/CDX9927R
35
XM_TX_OUT/
MIC_DET_OUT
O
Not used (Open)
36
XM_RX_IN/KRMOD
I
Not used (Open)
37
DVD XIFCS
I
Chip select signal output from CXD9917R/CDX9927R
38
MTK RST
O
System reset output
39
P_CONT1
O
Power control signal output
40
P_CONT2
O
Power control signal output
41
WRITE EMP
P_CONT3
O
Power control signal output
42
DRIVE_RST(EN)
O
D-AMP driver reset signal output
43
SD(DIAG)/PVDD_DET
I
D-AMP driver shut down signal input
44
OVERFLOW1
I
D-AMP processor F/C/S over fl ow detect signal input
45
OVERFLOW2
I
D-AMP processor SW over fl ow detect signal input
46
WRITE CE
I
Not used (Fixed to “H” (+3.3V))
47
I2C_DATA
I/O
EEPROM I2C serial data input/output
48
I2C_CLK
I/O
EEPROM I2C serial clock input/output
49
DAMP LATCH3
O
D-AMP processor latch-3 signal output
50
DAMP INIT
O
D-AMP processor reset signal output
51
DAMP SOFT MUTE
O
D-AMP processor soft mute signal output
MAIN BOARD (5/9) IC501 R5F3640DDFAR (SYSTEM CONTROL)
Ver. 1.1
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