Sony DAR-RD100 / SA-WSRD1 / SS-CTRD1 Service Manual ▷ View online
25
SA-WSRD1/SS-CTRD1
•
IC Pin Function Description
MAIN BOARD IC501 M30622MEP-A10FPU0 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT
O
Serial data output to the stream processor
2
DAMP_SHIFT
O
Shift clock signal output to the stream processor
3
NSP_MUTE
O
Muting on/off control signal output to the stream processor "L": muting on
4
SIRCS
I
Remote control signal input terminal
5
DSP_DOUT/
DIR_DOUT
O
Serial data output to the digital audio interface receiver and DSP
6
DSP_DIN
I
Serial data input from the DSP
7
DSP_CLK/
DIR_CLK
O
Serial data transfer clock signal output to the digital audio interface receiver and DSP
8
BYTE
-
Not used
9
CNVSS
-
Not used
10, 11
NO USE
-
Not used
12
RESET
I
System reset signal input terminal "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
13
XOUT
O
Main system clock output terminal (5 MHz)
14
VSS
-
Ground terminal
15
XIN
I
Main system clock input terminal (5 MHz)
16
VCC
-
Power supply terminal (+3.3V)
17
NMI
-
Not used
18
DIR_ZERO
I
Audio serial data input from the digital audio interface receiver
19
DIR_INT
I
Interrupt status input from the digital audio interface receiver
20
AC_CUT
I
AC cut detection signal input terminal "L": AC cut
21
NO USE
-
Not used
22
V CON
-
Not used
23 to 27
NO USE
-
Not used
28
SMST-SEL
-
Not used
29
I2C_CLK
-
Not used
30
I2C_DATA
-
Not used
31
STR_SOD
O
Serial data output terminal Not used
32
STR_SID
I
Serial data input from the main unit
33
STR_SCI
I
Serial data transfer clock signal input from the main unit
34
RTS1
-
Not used
35
FL_DATA
O
Serial data output to the FL driver
36
FL_STB
O
Chip enable signal output to the FL driver
37
FL_CLK
O
Serial data transfer clock signal output to the FL driver
38 to 40
NO USE
O
Not used
41
EPM
-
Not used
42
NO USE
-
Not used
43
P_CONT1
O
Power on/off control signal output to the regulator IC
44
P_CONT2
O
Power on/off control signal output to the regulator IC and power supply circuit
45
P_CONT3
O
Power on/off control signal output terminal Not used
46
CE
-
Not used
47
DRIVE_RST
(EN)
O
Reset signal output to the digital power amplifier "L": reset
48
DRIVE_OCP
(DIAG)
I
Shut down state input from the digital power amplifier "L": shut down
49
OVERFLOW1
I
Over flow status 1 input from the stream processor
26
SA-WSRD1/SS-CTRD1
Pin No.
Pin Name
I/O
Description
50
OVERFLOW2
I
Over flow status 2 input from the stream processor
51 to 53
DAMP LATCH1
to
DAMP LATCH3
O
Latch control signal output to the stream processor
54
DAMP_INIT
O
Reset signal output to the stream processor "L": reset
55
DAMP_SOFT_
MUTE
O
Soft muting on/off control signal output to the stream processor "L": muting on
56, 57
NO USE
-
Not used
58
DSP_ACK
I
Acknowledge signal input from the DSP
59
DSP_GP9
I
Read ready signal input from the DSP
60
DSP_XRST
O
System reset signal output to the DSP "L": reset
61
DSP_HCE
O
Chip select signal output to the DSP
62
VCC2
-
Power supply terminal (+3.3V)
63
DSP_BST
O
Boot strap signal output to the DSP
64
VSS
-
Ground terminal
65
DSP_PM
O
PLL initialize signal output to the DSP
66
DSP SKIP
O
Write enable signal output to the DSP
67
DIR_CE
O
Chip enable signal output to the digital audio interface receiver
68
DIR_ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
69
DIR UGIP
I
Source clock selection monitor input from the digital audio interface receiver
70
DTR DIN
I
Read data input from the digital audio interface receiver
71
DIR_RST
O
System reset signal output to the digital audio interface receiver
72
AD_RST
O
System reset signal output to the A/D converter
73
AUDIO SEL
-
Not used
74
KEY-INT
I
Key interruption processing start signal input terminal
75
RDS_CLK
I
RDS serial data transfer clock signal input from the tuner unit
76
RDS_DATA
I
RDS serial data input from the tuner unit
77
ST_CLK
O
PLL serial data transfer clock signal output to the tuner unit
78
ST_DI
I
PLL serial data input from the tuner unit
79
ST_CE
O
PLL serial chip enable signal output to the tuner unit
80
ST_DO
O
PLL serial data output to the tuner unit
81
TUNED
I
Tuning detection signal input from the tuner unit "L": tuned
82
NO USE
-
Not used
83
NO USE
-
Not used
84
STBY_LED
O
LED drive signal output of the standby indicator "L": LED on
85 to 91
NO USE
-
Not used
92
DESTINATION
I
Setting terminal for the destination
93
MODEL
I
Setting terminal for the model
94
KEY2
I
Key input terminal (A/D input) Not used
95
KEY1
I
Key input terminal (A/D input)
96
AVSS
-
Ground terminal
97
KEY0
I
Key input terminal (A/D input)
98
VREF
I
Reference voltage (+3.5V) input terminal
99
AVCC
-
Power supply terminal (+3.3V)
100
NO USE
-
Not used
27
SA-WSRD1/SS-CTRD1
MAIN BOARD IC506 CXD9862R (DSP)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
5
VDDI
-
Power supply terminal (+1.8V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input terminal Not used
7
PLOCK
O
PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.8V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock Fixed at "L" in this set
14
SCKOUT
O
Master clock signal output to the stream processor
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the digital audio interface receiver
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the stream processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the stream processor
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+1.8V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
48
VSS
-
Ground terminal
28
SA-WSRD1/SS-CTRD1
Pin No.
Pin Name
I/O
Description
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Output terminal for the test Not used
56
BST
I
Boot strap signal input terminal
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode
Fixed at "H" in this set
Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use
Fixed at "L" in this set
Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+1.8V)
61
VSS
-
Ground terminal
62
A17
O
Address signal output terminal Not used
63, 64
A16, A15
O
Address signal output to the S-RAM
65
A14
O
Address signal output terminal Not used
66
A13
O
Address signal output to the S-RAM
67
GP10
O
Not used
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
PCM audio data input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+1.8V)
71
VSS
-
Ground terminal
72 to 75
D15 to
D12
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11 to
D8
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+1.8V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
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