Sony D-F21 / D-F22ST / ICD-BP220 Service Manual ▷ View online
11
D-F21/F22ST
• IC801 TMP88CM22AF-3H31 (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1
VSS
—
Ground
2
PWRSW
O
Headphone AMP IC power switch signal output
3
FOK I
I
Focus OK signal input from DSP IC. (“L”: NG, “H”: OK)
4
AGCPWM O
O
AGC control pulse signal output (Not used in this set)
5
CDON O
O
CD ON request signal output
6
SWEN2 O
O
CD/tuner select signal output
7
AMUTE O
O
Analog audio mute ON/OFF control signal output
8
VCC2ON O
—
Power supply pin (Not used in this set)
9
XRST O
O
Reset signal output to DSP IC.
10
SCK O
O
Serial data transfer clock signal output to DSP IC.
11
(SENS) SDTI I
I
Serial data signal input from DSP IC.
12
SDTO O
O
Serial data signal output to DSP IC.
13
SLPOUT O
O
WAKE-UP control signal output
14
AD CDTEST
I
CD test signal input (“L”: CD test) (Fixed at “H” in this set)
15
AD CHGMNT
I
Not used in this set. (Open)
16
AD RMKEY
I
Not used in this set. (Fixed at “L”)
17
AD BATMNT
I
Battery voltage detect signal input
18
AD CDKEY
I
Key signal input
19
AD RM INT
I
Not used in this set. (Open)
20
AD DCINMNT
I
DC-in voltage detect signal input (A/D input) and DC-in jack use/no use detect signal input.
21
WP OPEN
I
CD door open switch signal input
22
VREFL
I
Reference voltage signal input (0 V) for A/D converter.
23
VREFH
I
Reference voltage signal input (+2 V) for A/D converter.
24
VDD
—
Power supply pin (+2 V)
25
SCOR I
I
Sub-code sync (S0+S1) detect signal input from DSP IC.
26
GRSCOR I
I
GRSCOR signal input from DSP IC.
27
WFCK I
I
WFCK signal input from DSP IC.
28
BEEP O
O
Beep sound signal output to headphone AMP IC.
29
XCDRESET TU O
O
Reset signal output to DSP IC.
30
TUSCK O
O
Communication clock signal output to DSP IC.
31
(CD) SDI I
I
Communication data bus signal input from DSP IC.
32
(CD) SDO O
O
Communication data bus signal output to DSP IC.
33
RESERVE
—
Not used. (Open)
34
ACK CD I
I
CD acknowledge signal input
35
TUON I
I
Tuner ON request signal input
36
ESP
I
ESP switch signal input
37
L/O I
I
Line out signal input
38
AVLS I
I
AVLS switch signal input
39
HOLD I
I
HOLD switch signal input
40
CD-RW
I
Not used in this set. (Open)
41
—
—
Not used. (Open)
42
XHGON O
O
Not used in this set. (Open)
43
XTL O
O
Serial data latch pulse signal output
44
XSOE O
O
Serial data output enable signal output
45
TUVCPU O
O
Not used in this set. (Open)
46
POWLT O
O
Latch signal output to power control IC.
47
TUAUDIO O
O
Not used in this set. (Open)
48
XAPC OFF O
O
APC mute signal output (“L”: mute)
49
CDAUDIO O
O
Not used in this set. (Open)
50
RESERVE
—
Not used. (Open)
12
D-F21/F22ST
Pin No.
Pin Name
I/O
Pin Description
51
BASS1 O
O
Not used. (Fixed at “H” in this set)
52
BASS2 O
O
Not used. (Fixed at “H” in this set)
53
LCDREQ O
O
LCD display request signal output
54 – 64
SEG10 – 0
O
Not used in this set. (Open)
65 – 68
COM3 – 0
O
Not used in this set. (Open)
69 – 71
V3 – 1
O
Not used in this set. (Open)
72, 73
C1, 0
O
Not used in this set. (Open)
74
CDWP I
I
WAKE-UP control signal input
75
ICTEST
I
Test pin for IC. (Fixed at “L” in this set)
76
—
—
Not used. (Open)
77
—
—
Not used. (Fixed at “L” in this set)
78
RESET I
I
System reset signal input from power control IC. (“L”: reset)
79
XIN I
I
System clock signal input
80
XOUT
O
Not used in this set. (Open)
D-F21/F22ST
13
13
5-2. BLOCK DIAGRAM — CD SECTION —
1
2
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR
IC601
13
97
104
94
93
83
78
28
26
30
35
24
25
23
3
27
26
11
44
43
10
12
25
21
LPF
SIGNAL
PROCESSOR
BLOCK
MEMORY
CONTROLLER,
BUS BOOST
BLOCK
SERVO
BLOCK
BLOCK
• Signal path
: CD PLAY
MDS
44
MDS
MDP
43
MDP
COMP OUT
SENS
SCOR
17
SCOR
42
11
12
10
C176
SDTO
XTAI
XTAO
RFAC
XSOE
R4M
XLAT
XLAT
CLOK
LOUT
ROUT
AMUTE
FOK
FOK
R4M
XSOE
WDCK
WFCK
SDTO
SENS
CLOK
XLA
T
XSOE_O
GRSCOR_I
FOK_I
WFCK_I
SDTO_O
SCOR_I
(SENS) SDTI_I
SCK_O
XLA
T_O
46
47
SFDR
XRST
RFDC
B
A
2
WDCK
WFCK
XTAO
XTAI
E
F
SRDR
TRDR
FRDR
FFDR
TFDR
FFDR
FRDR
59
F
62
61
A
B
58
71
RFDC
RFAC
E
50
51
SFDR
SRDR
48
49
35
36
13
14
61
TFDR
TRDR
OPTICAL PICK-UP
BLOCK (DAX-23E)
BLOCK (DAX-23E)
A
A
CN501
CN503
CN502
B
RF
E
F
B
RF
E
F
PD
PD
LD
LD
DETECTOR
VCC
FOCUS
COIL
TRACKING
COIL
FI2
RI2
33
34
FI1
RI1
FI3
SAW TOOTH
MDP
VINDET
RI3
15
PWM/FI4
16
PDL/RI4
APCREF
VCC1 +2V
FO2
RO2
FO3
RO3
RF2
INM2
RF21
PAPC
F+
F–
T+
T–
+
COMPARATOR
IC401 (2/3)
SYNC
48 XAPC_OFF_O
9
XRST_O
SDTO
SCK
SYSTEM CONTROL
IC801 (1/3)
X601
16.9MHz
CD-L
CD-R
A MUTE
B
C
A
60
28
26
23
21
63
64
59
M502
SPINDLE
MOTOR
FO4
RO4
M
C+
C–
19
17
DRIVER
DRIVER
CONTROLLER
DRIVER
PD AMP
LD AMP
LD
DRIVER
Q403,405
LEVEL
SHIFTER
60
FOCUS/TRACKING COIL DRIVER,
SPINDLE/SLED MOTOR DRIVE
IC401 (1/3)
B+ +3V
62
D
115 – 118
113
114
119
120
XRAS
XWE
XCAS
XOE
D0-D3
A0-A9
4
10
1-3, 5-7, 106-109
79
XIN_I
M501
SLED
MOTOR
FO1
RO1
M
S+
S–
32
30
DRIVER
13
12
11
7
8
6
4
1
2
3
10
9
1
2
MAIN BOARD (1/3)
(Page 15)
(Page 15)
(Page 15)
(Page
14)
14)
D-F21/F22ST
14
14
5-3. BLOCK DIAGRAM — TUNER SECTION —
Signal path
: FM
: AM
: CD PLAY
: FM
: AM
: CD PLAY
Abbreviation
E13 : AC220-230V area in E model
E13 : AC220-230V area in E model
AM
OSC
AM
MIX
FM
MIX
FM
OSC
AM
RF-IN
RF-IN
FM
RF-IN
RF-IN
FM
RF-OUT
RF-OUT
16
15
12
11
20
22
4
6
7
10
2
21
19
24
T1
CF1
L2
L1
CT1
VCPU+2V
XDCDT
D1
D2
CT3
D3
L3
AM
FERRITE-ROD
ANTENNA
CT3,L4
AM
TRACKING
CT1,L2
FM
TRACKING
BUFFER
Q61
AM
DET
FM
DET
AF
BUFFER
DC/DC
CONVERTER
Q86
IF
BUFFER
FM
MPX
MUTE
IF CUT
R-CH
L-OUT
R-OUT
R-CH
VDD+2V
R-CH
D601
D304
D302
17
FM/AM FRONT-END,
IF DET,MPX
IC1
TU VCC
TU VCC
Q3
Q6
Q2
TU VCC
L4
CF3
IF CUT
TU VCC
TU VCC
FM OSC
AM OSC
MIX-OUT
AM
IF-IN
IF-IN
FM
IF-IN
IF-IN
DET-OUT
MPX-IN
T1
AM IF
LIN
HEADPHONE AMP
IC302
14
LOUT
8
PWRSW
MUTE
19
BEEP
ALCDET
17
PW SW
BEEP
MT SW
20
TUNER/CD
SIGNAL SELECT
IC303
8
9
12
6
11
IF OSC
AMP
Q60
LPF
Q84,85
5 – 20
1 – 4
LIQUID CRYSTAL
DISPLAY PANEL
LCD1
COM1
|
COM4
S1
|
S16
22 23
24
74
75
45
32
31
30
1
2
3
25
55
65
53
71
70
61
64
59
6
7
2
28
21
36
62 49 29
73
54
33
38
39
46
47
48
51
52
42
29
74
37
34
5
32
31
30
39
38
18
21
44
X61
75kHz
(EXCEPT F21:E13)
(F21:E13)
(EXCEPT F21:E13)
(F21:E13)
X1
10.7MHz
TU VCC
TU VCC
ST OR DX-O-CTR
XDC IN
DET-I
EO(DO1)
AM IN
FM IN
60
+B ON/OFF-O
DEST2-I
DEST1-I
DEST0-I
XOUT
CS
SK
DI
XIN
AD DC REF
EEP CS-O
EEP SK-O
EEP DO/D1-IO
XLOCAL/XMONO-DET-I
AM STEP-I
IFREQ-O
IF IN
IF-OUT
OSC-OUT
LPF2(MAX/FM)
LPF1(MONO/ST)
AM/XFM-O
TUMUTE-O
TUBEEP-O
LID OPEN
HOLD
AVLS
SWEN2_O
AMUTE_O
PWRSW
BEEP_O
RESET
XCDRESET_TU-O
CDWP_I
L/O_I
L/O_I
ACK_CD_I
CDON_O
CDON_O
(CD)SDO_O
(CD)SDI_I
TUSCK_I
HOLD_I
AVLS_I
AVLS_I
AD3_BATT_HIDC
AD_CDKEY
SDI-I-CDU
SDO-O-CDU
SCK-I-CDU
XHOLD-I-SW
XAVLS-I-SW
AD1_KEY
HIGH/BATT
TU ON-O
XL/O-I
CD ACK-I
WP_OPEN
ESP
CDON-IWP-CDU
12
10
13
14
+1.6V REG.
IC81
B+ SWITCH
Q4,5
B+ +3V
VCPU+2V
TU VCC
S813
S812
STEP
STEP
9k
10k
AVLS
S802
S801
(CD DOOR OPEN)
VCPU+2V
OPEN
AVLS
HOLD
NORM
LIMIT
HOLD
S803
OFF
ON
ESP
S804
OFF
ON
MONO
ST
R-CH
A MUTE
CD-L
CD-R
T81
D80
KEY MATRIX
S805 - 811
VOLUME
RV301
D
E
F
MAIN BOARD (2/3)
EEPROM
IC62
VCPU
TUNER PLL,
LCD DRIVER
IC61
OPEN
SYSTEM CONTROL
IC801 (2/3)
J302
i
EXCEPT
F21:E13
(F21:E13)
(
)
Q1
LOCAL
DX
(Page 13)
(Page 15)
(Page 15)
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