Sony CX-LMN5 / XR-MN5 Service Manual ▷ View online
42
42
CX-LMN5
8-14. Schematic Diagram — Main Section 6/Power Section —
D251
D252
D253
D254
D255
JW201
CN252
CN251
CN253
C251
RY252
C250
RY251
C253
CN202
PT251
CN255
CN254
CN256
CN257
CN250
WH250
R254
JW271
S250
PT252
PT253
JW252
JW251
1SS133T-72
1SS133T-72
1SS133T-72
1SS133T-72
1SS133T-72
0
3P
2P CONN ASSY
3P CONN ASSY
0.0022
250V
G5PA-2
0.0022
250V
G5PA-1-M
AC 9V
0.0022
250V
2P
SUB PT(TAM)
3P CONN ASSY
2P
3P
7P
WIRE ASSY 7P
TID-A
HLDR WIRE 2.5-7P
2.2M
1/2W
1/2W
0
0
0
C254
AEP,KR,TH
US,CND,AEP,UK,TH
SP,TW,AUS
E,SP,TW,AUS
E,SP,AUS
EXCEPT E,SP,TW,AUS
E
0.1
Ver 1.1 2003. 06
43
43
CX-LMN5
8-15. Printed Wiring Boards — Power Section —
• See page 27 for Circuit Boards Location.
(US,CND)
36
36
36
36
36
C254
US,CND,AEP,UK,TH
EXCEPT US,CND,AEP,UK,TH
SP,TW,AUS
E
KR
C254
AEP,TH
1
2
A
B
C
D
3
4
5
6
7
9
8
10
11
•
: Uses unleaded solder.
Ver 1.1 2003. 06
44
44
CX-LMN5
8-16. IC Block Diagrams
— BD Board —
IC101 CXD3068Q
IC102 AN41020A
IC103 CXA2647N-T4
CE
RFDC
AD
IO
IGEN
ASYO
ASYI
RFAC
CLTV
FILO
FILI
PCO
BIAS
VCTL
V16M
VPCO
TE
ASYE
MD2
DOUT
DOUT
LR
CK
PCM
D
BC
K
EM
PH
XTSL
XTAI
XTAO
SOUT
SOCK
XOLT
SOCK
XOLT
SQSO
SQCK
SQCK
SCSY
SBSO
EXCK
EXCK
XRST
M
U
TE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
W
FCK
XU
G
F
XPCK
G
FS
C2PO
SCOR
CAM
W
D
CK
COUT
MIRR
SE
FE
VC
FE
VC
TES1
TEST
TEST
FFDR
TRDR
TFDR
SRDR
SFDR
FSTO
SSTP
LOCK
PWMI
PWMI
FOK
FRDR
MDP
DFCT
CLOCK
GENERATOR
ASYMMETRY
CORRECTOR
CORRECTOR
DIGITAL
PLL
CPU
INTERFACE
INTERFACE
CORRECTOR
PROCESSOR
SUB CODE
RAM
32K
DEMODURATOR
EFM
ERROR
D/A
DIGITAL
OUT
INTERFACE
SERVO
INTERFACE
SERVO
AUTO
MIRR
DFCT
DFCT
FOK
SERVO
FOCUS
SERVO DSP
SERVO
SERVO
SLED
TRACKING
FOCUS PWM
GENERATOR
GENERATOR
GENERATOR
GENERATOR
SLED PWM
TRACKING PWM
A/D
CONVERTER
OPAMP
ANALOG SW
PWM GENERATOR
DIGITAL
CLV
SERVO BLOCK
1
2
3
4
5
6
7
9
8
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
16
17
18
19
20
15
14
13
12
11
10
PGND1
PGND1
DIRECTION
DETECTION
DIRECTION
DETECTION
RESET CIRCUIT
.STANDBY
.BAND-GAP
.SVCC
DIRECTION
DETECTION
DIRECTION
DETECTION
PVCC/2
PVCC/2
PVCC/2
PVCC1
PVCC1
VO2+
VO1+
VO1-
IN1+
IN1-
OPO1
OPO2
SGND
IN2+
IN2-
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VO2-
PGND2
PGND2
ST
ANDBY
PVCC2
PVCC2
VO3-
VO4-
VO4+
VREF
IN4
IN4R
IN3+
SVCC
OPO3
IN3-
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VO3+
ROM/RW
ROM/RW
RF OFF AT VCC
VOFST
VOFST
DVC
VC
VC
VC
ROM/RW
VC
VC
30
29
28
+
–
+
–
VC
VCC
DVC
27
26
25
24
ROM/RW
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
ROM/RW
VC
ROM/RW
DVC
+
–
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
ROM/RW
DVC OR Hi-Z
SLEEP, APC OFF
VOFST
VC
ROM/RW
+
–
10
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDC
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
VC
+
–
VC
+
–
11
GM
F
GM
ROM/RW
(L/H)
VOFST
45
CX-LMN5
IC104 TC94A20F-CX4
33
34
35
36
37
38
39
40
41
42
1
8
43
61
62
63
64
60
59
56
52
50
47
46
45
44
48
49
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
2
3
4
5
6
7
58
57
55
53
51
12
13
14
15
16
54
PO2
PO3
VDDT
PO1
PO0
TXO
TESTP
VSSR
DIT
DAC
DAC
Bus
Switch
PO4
PO5
PO6
MP3REQ
Gener
al
Output P
o
rt
Address Calc.
2sets
Y-
P
ointer
register
C-P
ointer
register
X-P
ointer
register
VSS
IRQ
VDDM
FI0
FI1
Flag
ERAM
2k w
ord
CR
OM
4k w
ord
YRAM
4k w
ord
XRAM
4k w
ord
Timer
Interr
upt
Control
DRAM I/F
I-Bus
SRAM I/F
1Mbit
SRAM
X-Bus
Y
-Bus
PI0
PI1
VSS
VSSM
General
Input Port
SubQ
I/F
VC0
Timing
Generator
PRAM
256 w
ord
PR
OM
1k
=12k w
ord
10bit
Instr
uction
Decoder
Prog
ra
m
Control
Microcom.
I/F
register
XO • X1 • X2
Y0 •
Y1 •
Y2
MX
MY
MZ
MA
C
A0
A1
AX
A
Y
ALU
A2
A3
round & limit
round & limit
A
udio I/F
BCKIB
SDI1
LRCKIA
BCKIA
SDIO
LRCKO
BCKO
SDO
VDDT
/MIACK
/MICK
MIDIO
/MILP
/MICS
MIMD
/RESET
PI2
PI3
PI4/CLCK
VDD
PI5/D
A
T
A
TSTIN/SFSY
FI2/SBSY
VSSP
PDO
VCOI
VDDX
VSSX
CK
O
VDDP
XI
XO
VRAR
RO
VD
AR
VD
AL
LO
VRAL
VSSL
VSS
ST
ANDBY
VDD
LRCKIB
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