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54
CX-JV4
•
VMP50 BOARD IC801 ES3880FM (VIDEO CD MPEG PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDD3
—
Power supply terminal (+3.3V)
2
RAS
O
Row address strobe signal output to the D-RAM
3
DWE
O
Write enable signal output to the D-RAM
4 to 12
MA0 to MA8
O
Address signal output to the D-RAM
13 to 28
DBUS0 to
DBUAS15
I/O
Two-way data bus with the D-RAM
29
RESET
I
Reset signal input from the MPEG video/audio decoder “L”: reset
30
GND
—
Ground terminal
31
VDD3
—
Power supply terminal (+3.3V)
32 to 39
YUV0 to YUV7
O
YUV 8-bit video data bus output to the MPEG video/audio decoder
40
VSYNC
I
Vertical sync signal input from the MPEG video/audio decoder “L”: active
41
HSYNC
I
Horizontal sync signal input from the MPEG video/audio decoder “L”: active
42
DCLK
I
System clock signal input from the MPEG video/audio decoder
43
PCLK2X
I
27 MHz pixel clock signal input from the MPEG video/audio decoder
44
PCLK
I
13.5 MHz pixel clock signal input from the MPEG video/audio decoder
45
AUX0
I
Guard frame sync signal input from the digital signal processor
46
AUX1
I
Focus OK signal input from the digital signal processor
47
CD ACK
O
Acknowledge signal input from the system controller
48
AUX3
O
Serial data transfer clock signal output to the digital signal processor
49
AUX4
O
Interrupt request signal output to the MPEG video/audio decoder
50
GND
—
Ground terminal
51
VDD3
—
Power supply terminal (+3.3V)
52
AUX6
O
Strobe signal output to the system controller
53
AUX5
O
Strobe signal output to the MPEG video/audio decoder
54
AUX7
O
Serial data output to the system controller
55 to 62
LD0 to LD7
I/O
Two-way data bus with the MPEG video/audio decoder Data input from the program ROM
63
LWR
O
Write enable signal output terminal Not used
64
LOE
O
Output enable signal output to the program ROM
65
LCS3
O
Chip enable signal output to the program ROM
66
LCS1
O
Clock signal output to the MPEG video/audio decoder
67
LCS0
O
Chip select signal output terminal Not used
68 to 79
LA12 to LA17
O
Address signal output to the program ROM
80
GND
—
Ground terminal
81
VDD5
—
Power supply terminal (+5V)
82 to 87
LA0 to LA11
O
Address signal output to the program ROM
88
ACLK
O
Master clock signal output to the MPEG video/audio decoder
89
AOUT/
SELPLL0
O
Audio data output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
90
ATCLK
O
Audio bit clock signal (2.8224 MHz) output to the MPEG video/audio decoder
91
ATPS/
SELPLL1
O
Audio frame sync signal output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
92
DOE
O
Output enable signal output to the D-RAM
93
AIN
I
Audio serial data input from the MPEG video/audio decoder
94
ARCLK
I
Audio bit clock signal (2.8224 MHz) input from the MPEG video/audio decoder
95
ARFS
I
Audio frame sync signal input from the MPEG video/audio decoder
55
CX-JV4
Pin No.
Pin Name
I/O
Description
96
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
97
PCMD
I
Serial data input from the digital signal processor
98
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
99
CAS
O
Column address strobe signal output to the D-RAM
100
GND
—
Ground terminal
56
CX-JV4
•
VMP50 BOARD IC802 ES3889 (MPEG VIDEO/AUDIO DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
GND
—
Ground terminal
3
NC
—
Not used
4, 5
VDD
—
Power supply terminal (+5V)
6
DSC-C
I
Clock signal input from the video CD MPEG processor
7
AUX00
I
Video system select switch input terminal “L”: PAL, “H”: AUTO or NTSC
8
DSCD0
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
9
AUX01
I
Video system select switch input terminal “L”: NTSC, “H”: PAL or AUTO
10
DSC-C
I
Strobe signal input from the video CD MPEG processor
11
AUX02
O
Serial data load output to the D/A converter
12
DCLK
O
System clock signal output to the video CD MPEG processor
13
RST
I
Reset signal input terminal “L”: reset
14
AUX07
I
Internal status (SENSE) signal input from the digital signal processor
15
MUTE
O
Audio muting on/off control signal output terminal Not used
16
VDD
—
Power supply terminal (+5V)
17
MCLK
I
Audio master clock signal input from the video CD MPEG processor
18
AUX08
O
Laser diode on/off control signal output to the RF amplifier “L”: laser diode on
19
TWS
I
Audio frame sync signal input from the video CD MPEG processor
20
AUX09
I/O
Subcode Q data input from the video CD MPEG processor
21
TSD
I
Audio data input from the video CD MPEG processor
22
TBCK
I
Audio bit clock signal (2.8224 MHz) input from the video CD MPEG processor
23
PWS/SPLL1
I/O
Audio frame sync signal output to the video CD MPEG processor
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at “H” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at “H” in this set)
24
RSTOUT
O
Reset signal output to the video CD MPEG processor “L”: reset
25, 26
GND
—
Ground terminal
27, 28
NC
—
Not used
29 to 31
GND
—
Ground terminal
32
VDD
—
Power supply terminal (+5V)
33
RSD/SPLL0
I/O
Audio data output to the video CD MPEG processor
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at “L” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (pin qs) output
(fixed at “L” in this set)
34
AUX10
O
Reading clock signal output to the digital signal processor
35
AUX11
I
Interrupt request signal input from the video CD MPEG processor
36
AUX12
I
C2 pointer signal input from the digital signal processor
37
RBCK/SER IN
I/O
Audio bit clock signal (2.8224 MHz) output to the video CD MPEG processor
Selection signal input terminal for the serial input DSC mode
“L”: parallel DSC mode, “H”: serial DSC mode (fixed at “L” in this set)
Selection signal input terminal for the serial input DSC mode
“L”: parallel DSC mode, “H”: serial DSC mode (fixed at “L” in this set)
38
AUX13
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
39
AUX14
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
40
AUX15
I
Serial data input from the system controller
41
AGND
—
Ground terminal (analog system)
42
VREFM
I
Not used
43
VREFP
I
Not used
44
AVDD
—
Power supply terminal (+5V) (analog system)
45
AOR+
O
Audio data (R-ch) output to the electrical volume
46
AOR–
O
Audio data (R-ch) output to the electrical volume
47
AOL+
O
Audio data (L-ch) output to the electrical volume
57
CX-JV4
Pin No.
Pin Name
I/O
Description
48
AOL–
O
Audio data (L-ch) output to the electrical volume
49, 50
MIC2, MIC1
I
MIC signal input terminal Not used
51
AGND
—
Ground terminal (analog system)
52
VREF
I
Not used
53
VCM
I
Not used
54
RSET
I
Not used
55
COMP
I
Not used
56, 57
VGND
—
Ground terminal (video analog system)
58
CDAC
O
Modulated chrominance output terminal Not used
59, 60
VVDD
—
Power supply terminal (+5V) (for video)
61
YDAC
O
Y luminance data bus terminal Not used
62, 63
VGND
—
Ground terminal (video analog system)
64
VDAC
O
Composite video signal output terminal
65
ACAP
I
Not used
66
VDD
—
Power supply terminal (+5V)
67
AUX06
O
Serial data latch pulse signal output to the digital signal processor
68
AUX05
O
Serial data latch pulse signal output to the digital signal processor and D/A converter
69
AUX04
O
Laser diode on/off control signal output to the RF amplifier “L”: laser diode on
70
AUX03
I/O
Not used
71
XOUT
O
System clock output terminal (27 MHz)
72
GND
—
Ground terminal
73
VDD
—
Power supply terminal (+5V)
74
XIN
I
System clock input terminal (27 MHz)
75
GND
—
Ground terminal
76
NC
—
Not used
77
GND
—
Ground terminal
78
VDD
—
Power supply terminal (+5V)
79
PCK
O
13.5 MHz pixel clock signal output to the video CD MPEG processor
80
PCK2
O
27 MHz pixel clock signal output to the video CD MPEG processor
81
DSCD7
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
82
HSYNC
O
Horizontal sync signal output to the video CD MPEG processor “L”: active
83
DSCD6
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
84
VSYNC
O
Vertical sync signal output to the video CD MPEG processor “L”: active
85
DSCD5
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
86 to 89
YUV7 to YUV4
I
YUV 8-bit video data bus input from the video CD MPEG processor
90
VDD
—
Power supply terminal (+5V)
91
GND
—
Ground terminal
92
YUV3
I
YUV 8-bit video data bus input from the video CD MPEG processor
93
DSCD4
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
94
YUV2
I
YUV 8-bit video data bus input from the video CD MPEG processor
95
DSCD3
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
96
YUV1
I
YUV 8-bit video data bus input from the video CD MPEG processor
97
DSCD2
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
98
YUV0
I
YUV 8-bit video data bus input from the video CD MPEG processor
99
DSCD1
I/O
Two-way data bus with the video CD MPEG processor Data input from the program ROM
100
GND
—
Ground terminal
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