Sony CX-JD5 / JAX-D5 Service Manual ▷ View online
85
CX-JD5
Pin No.
Pin Name
I/O
Description
168
VSS
—
Ground
169
XTA2
O
System clock output (33.8688 MHz)
170
XTA1
I
System clock input (33.8688 MHz)
171
VDD
—
Power supply (+3.3V)
172 to 176
D0 to D4
I/O
Two-way data bus with the CXP973064-226R
86
CX-JD5
•
MB03 BOARD IC901 CXP973064-232R (MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NO_USE
O
Not used
2
SDEN
O
Serial data enable signal output to SP3723BDAOPM
3
DOCTRL
O
Digital out on/off control signal output to CXD3068Q
4
XRST_2753
O
Not used
5
SDA_EEP
I/O
Data bus with the EEPROM
6
MNT1
I
EEPROM ready signal input from TMC57929PGF-RDP
7
FCS_JMP_1
O
Focus jump 1 signal output to the FAN8035L
8
FCS_JMP_2
O
Focus jump 2 signal output to the FAN8035L
9
SENS_CD
I
Internal status (SENSE) signal input from CXD3068Q
10
CDSP2
O
Not used
11
CDSP4
O
Not used
12
XCS_DVD
O
Chip select signal output to TMC57929PGF-RDP
13
VSS
—
Ground
14 to 21
D0 to D7
I/O
Two-way data bus with TMC57929PGF-RDP
22
INIT0_DVD
I
Interrupt signal input from TMC57929PGF-RDP
23
INIT1_DVD
I
Interrupt signal input from TMC57929PGF-RDP
24
MSCK_SAMBA
O
Not used
25
XRST_1882
O
Reset signal output to TMC57929PGF-RDP
26
SCOR
I
Subcode sync (S0+S1) detection signal input from CXD3068Q
27
LAT_CD
O
Serial data latch pulse signal output to CXD3068Q
28
LD ON
O
Laser diode on/off control signal output to SP3723BDAOPM
29
MIRR
I
Mirror signal input from SP3723BDAOPM
30
COUT_CD
I
Numbers of track counted signal input from SP3723BDAOPM
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS_ZIVA
O
Chip select signal output to ZIVA5X-C1F
33
SI_ZIVA
I
Serial data input from ZIVA5X-C1F
34
SO_ZIVA
O
Serial data output to ZIVA5X-C1F
35
SCK_ZIVA
O
Serial data transfer clock signal output to ZIVA5X-C1F
36
DRVIRQ
O
Interrupt request signal output to ZIVA5X-C1F
37
DRVRDY
O
Ready signal output to ZIVA5X-C1F
38
RST
I
System reset signal input from ZIVA5X-C1F
39
VSS
—
Ground
40
XTAL
I
System clock input terminal (20 MHz)
41
EXTAL
O
System clock output terminal (20 MHz)
42
VDD
—
Power supply (+3.3V)
43, 44
SLED_A, SLED_B
O
Sled motor drive signal output to FAN8035L
45
SCK_DSD
O
Clock output to TMC57929PGF-RDP
46
SDOUT_DSD
O
Serial data output Not used
47
SDIN_DSD
I
Serial data input Not used
48
READY_DSD
I
Ready signal input Not used
49
DATA_CD
O
Serial data output to CXD3068Q
50
CLOK_CD
O
Serial data transfer clock signal output to CXD3068Q
51
XMSLAT
O
Serial data latch pulse signal Not used
52
SQSO
I
Subcode Q data input from TMC57929PGF-RDP
53
MUTE_DSD
O
Muting on/off control signal Not used
87
CX-JD5
Pin No.
Pin Name
I/O
Description
54
SQCK
O
Subcode Q data reading clock signal output to TMC57929PGF-RDP
55
VSS
—
Ground
56
CONTROL_2
I
Not used
57
CONTROL_1
I
Not used
58
GFS_DVD
I
Guard frame sync signal input from TMC57929PGF-RDP
59
MUTE_CD
O
Muting on/off control signal output to CXD3068Q
60
MUTE_2D
O
Muting on/off control signal output to FAN8035L
61
SLED
I
Sled motor servo drive PWM signal input from CXD3068Q
62
FG
I
Spindle motor control signal input from SP3723BDAOPM
63
SP_ON
O
Muting on/off control signal output to FAN 8035L
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input from SP3723BDAOPM
66
PI
I
Pull in signal input from SP3723BDAOPM
67
FE
I
Focus error signal input from SP3723BDAOPM
68
AVSS
—
Ground
69
AVREF
I
Reference voltage input (for A/D converter)
70
AVDD
—
Power supply (+3.3V) (for A/D converter)
71
GFS_CD
I
Guard frame sync signal input from CXD3068Q
72
SCLK_CD
O
SENSE serial data reading clock signal output to CXD3068Q
73
TSD-M
O
Thermal shut down signal output to FAN8035L
74
FOK_CD
I
Focus OK signal input from CXD3068Q
75
LOCK_CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output
78
I2C_SIO
I/O
Communication data bus input/output
79
I2C-SCL
I/O
Communication data reading clock signal input/output
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
SDCLK_RF
O
Serial data transfer clock signal output to SP3723BDAOPM
83
SDATA_RF
I/O
Two-way data bus with SP3723BDAOPM
84
XWR
O
Write strobe signal output to TMC57929PGF-RDP
85
XRD
O
Read strobe signal output to TMC57929PGF-RDP
86
(PWE)
—
Not used
87
VDD
—
Power supply (+3.3V)
88
VSS
—
Ground
89 to 96
A0 to A7
O
Address signal output to TMC57929PGF-RDP
97
A8
O
Motor/coil driver power save control signal Not used
98
XDRST
O
Reset signal output
99
WP_EEP
O
Write protect signal output to the EEPROM
100
CLK_EEP
O
Clock signal output to the EEPROM
88
CX-JD5
•
MAIN BOARD IC1104 M30620MCN-A29FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
S-OUT
O
Serial data output to the front panel controller
2
S-CLK
O
Serial data transfer clock signal output to the front panel controller
3
61530-CLK
O
Serial data transfer clock signal output to the M62530FP-D60G
4
SIRCS
I
Remote control signal input from the remote control receiver
5
61530-DAT
O
Serial data output to the M62530FP-D60G
6
61529-DAT
O
Serial data output to the M62529FP-D60G
7
61529-CLK
O
Serial data transfer clock signal output to the M62529FP-D60G
8
BYTE
I
External data bus line byte selection signal input terminal “L”: 16 bit, “H”: 8 bit (fixed at “L”)
9
CNVSS
—
Not used
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset switch “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
13
XOUT
O
Main system clock output terminal (16MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input Fixed at “H” in this set
18
AC-CUT
I
AC off detection signal input from the level detect “L”: AC cut checked
19
VIDEO-OUT-SW
O
Video out select signal output terminal “H”: DVD mode, “L”: other mode Not used
20
RDS-INT
I
Serial data reading clock signal input terminal Not used
21
RDS-DATA
I
Serial data input terminal Not used
22
ST-MUTE
O
Tuner muting control signal output to the FM/AM tuner unit “L”: muting on
23
STEREO
I
FM stereo detection signal input from the FM/AM tuner unit “L”: stereo
24
TUNED
I
Tuning detection signal input from the FM/AM tuner unit “L”: tuned
25
ST-CE
O
PLL serial chip enable signal output to the FM/AM tuner unit
26
ST-DOUT
O
PLL serial data output to the FM/AM tuner unit
27
ST-DIN
I
PLL serial data input from the FM/AM tuner unit
28
ST-CLK
O
PLL serial data transfer clock signal output to the FM/AM tuner unit
29
IIC-CLK
I/O
IIC data reading clock signal input or transfer clock signal output
30
IIC-DAT
I/O
IIC two-way data bus
31
SYS-POWER
O
CD/DVD power on/off control signal output terminal “H”: CD on
32
SYS-RESET
O
System reset signal output to the ZIVA5X-CIF
33
M-REQ
I
DAC muting request signal input from the ZIVA5X-CIF
34, 35
VIDEO-MUTE1,
VIDEO-MUTE2
O
Video muting on/off control signal output terminal “L”: muting on
36
DAC-MUTE
O
Muting on/off control signal output “L”: muting (front speaker)
37
SURROUND-MUTE
O
Muting on/off control signal output “L”: muting (surround speaker)
38
CENTER-MUTE
O
Muting on/off control signal output “L”: muting (center speaker)
39 to 41
I-BASS F3 to
I-BASS F1
O
I-BASS f0 control signal output terminal
42
I-BASS +10dB
O
I-BASS +10db control signal output terminal
43
I-BASS +8dB
O
I-BASS +8db control signal output terminal
44
I-BASS +6dB
O
I-BASS +6db control signal output terminal
45
I-BASS +5dB
O
I-BASS +5db control signal output terminal
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