DOWNLOAD Sony CMT-SV2D / HCD-SV2D Service Manual ↓ Size: 7.03 MB | Pages: 72 in PDF or view online for FREE

Model
CMT-SV2D HCD-SV2D
Pages
72
Size
7.03 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
cmt-sv2d-hcd-sv2d.pdf
Date
PREV: Sony CMT-SV2D Service Manual

Sony CMT-SV2D / HCD-SV2D Service Manual ▷ View online

49
HCD-SV2D
Pin No.
Pin Name
I/O
Description
110
MEMDA14
I/O
Flash memory data bus
111
MEMDA3
I/O
Flash memory data bus
112
MEMDA15
I/O
Flash memory data bus
113
MEMDA4
I/O
Flash memory data bus
114
GNDP
—
Ground terminal
115
MEMDA8
I/O
Flash memory data bus
116
VDDP
—
Power supply terminal (+3.3V)
117
MEMDA5
I/O
Flash memory data bus
118
MEMDA9
I/O
Flash memory data bus
119
MEMDA6
I/O
Flash memory data bus
120
MEMDA10
I/O
Flash memory data bus
121
MEMDA7
I/O
Flash memory data bus
122
MEMDA11
I/O
Flash memory data bus
123
MFWOS2
I
SCDVD signal input from the AV decoder
124
MEMCS1
—
Not used
125
GNDP
—
Ground terminal
126
MEMCS0
—
Not used
127
VDDP
—
Power supply terminal (+3.3V)
128
MEMRD
I
RD signal input from the AV decoder
129
MEMWR
I
WR signal input
130
VDDC
—
Power supply terminal (+1.8V)
131
MEMAD0
O
Flash memory address bus
132
GNDC
—
Ground terminal
133 to 138
MEMAD1 to 6
O
Flash memory address bus
139
GNDP
—
Ground terminal
140
MEMAD7
O
Flash memory address bus
141
VDDP
—
Power supply terminal (+3.3V)
142 to 146
MEMAD8 to 12
O
Flash memory address bus
147 to 150
MEMAD13 to 16
O
Flash memory address bus
152
MEMAD14
O
Flash memory address bus
153
VDDP
—
Power supply terminal (+3.3V)
154
MEMAD15
O
Flash memory address bus
155
MEMAD16
O
Flash memory address bus
156
VDDA
—
Power supply terminal (+1.8V)
157
RESET
I
Reset signal input
158
GNDA
—
Ground terminal
159
VDDP
—
Power supply terminal (+3.3V)
160
XO
O
System clock output (27MHz)
161
GCLKP
I
System clock input (27MHz)
162
GCLKA
I
System clock input (27MHz)
163
VDDADC
—
Power supply terminal (+3.3V)
164
SERADC2
—
Not used
165
SERADC1
—
Not used
166
SERADC0
—
Not used
167
GNDADC
—
Ground terminal
168
DACGNDD
—
Ground terminal
169
CVBS/C/Y
O
Video signal output
170
CVBC/C
O
Video signal output
171
DACVDD
—
Power supply terminal (+5V)
50
HCD-SV2D
Pin No.
Pin Name
I/O
Description
172
Y/R/V
O
Video signal output
173
C/B/V
O
Video signal output
174
DACGNDB
—
Ground terminal
175
RSET
I
Not used in this set.   Fixed at (“L”).
176
DACGNDDP
—
Ground terminal
177
GPCIO18
O
SPDIF (DVD/CD) change signal output
178
GNDP2
—
Ground terminal
179
AMCLK
I
AMCLK signal input from the AV decoder
180
VDDP2
—
Power supply terminal (+3.3V)
181
SPDIF/AOUT3
O
SPDIF DVD signal output
182
GPAIO
I
Not used in this set.   Fixed at (“L”).
183
GNDC
—
Ground terminal
184
AOUT O
O
Signal output to the audio DAC
185
VDDC
—
Power supply terminal (+1.8V)
186
AOUT 1
O
Not used in this set.   Fixed at (“L”).
187
AOUT 2
O
Not used in this set.   Fixed at (“L”).
188
ALR  CLK
O
LRCK signal output to the audio DAC
189
GNDP
—
Ground terminal
190
AB CLK
O
BCK signal output to the audio DAC
191
VDDP
—
Power supply terminal (+3.3V)
192
AIN
—
Ground terminal
193
LLCFGA
O
Video signal output terminal (D1/S) change signal output
194
LLCFGP
O
Line3 control signal output
195
GPCI017
O
SDA signal output to the EEPROM
196
GPCI016
O
SCL signal output to the EEPROM
197
GPCI015
O
Not used in this set.   Fixed at (“H”).
198
ICE TCK
I
Not used in this set.   Fixed at (“L”).
199
ICETDI/CPCIO24
—
Not used
200
IECTDO
O
S-VIDEO/RGB-SW  control signal output
201
IECTDI
O
SI-SW control signal output
202
JTMS/CPCIO46
—
Not used
203
JTMS/CPCIO47
O
Latch enable signal output to the audio DAC
204
JTDI/PUPRD
I
Not used in this set.   Fixed at (“H”).
205
JTDO/PUPTD
I
Not used in this set.   Fixed at (“H”).
206
TESTMODE
I
Not used in this set.   Fixed at (“L”).
207
GNDP
—
Not used
208
DUPTD
I
Not used in this set.   Fixed at (“H”).
51
HCD-SV2D
Pin No.
Pin Name
I/O
Description
1
ADI
O
Motor Drive AMP signal output
2
ADO
I
Motor Drive KFG signal input
3
JV
I
ADJV signal input
4
PREC
I
Reference signal input from the RF AMP
5
RF PH
I
RF peak signal input from the RF AMP
6
RF BH
I
Bottom signal input from the RF AMP
7
TE
I
Tracking error signal input from the RF AMP
8
FE
I
Focus error signal input from the RF AMP
9
TEST0
—
Ground terminal
10
EFNINP
I
DVD (RF) signal input from the RF AMP
11
TEST1
—
Ground terminal
12
EFNINN
I
DVD (RF) signal input from the RF AMP
13
SLCLPFO
O
SLC signal output
14
SLCLPFI
I
SLC signal input
15
SLCO1
I
SLC signal input
16
SLCO2
I
SLC signal input
17
ADVV1
—
Power supply terminal (+3.3V)
18
AVSS
—
Ground terminal
19
BHC
I
RF bottom signal input from the RF AMP
20
WO
I
WO signal input from the RF AMP
21
TEC
I
Tracking error signal input from the RF AMP
22
VREF
O
Motor Drive AMP signal output
23
TSTD1
I
Pick up signal input
24
TSTD0
I
Pick up signal input
25
FO
O
FO control signal output to the RF AMP
26
BST
O
BST control signal output to the RF AMP
27
TBAL
I
CP signal input from the RF AMP
28
FBAL
O
FE balance control signal output to the RF AMP
29
SGC
O
Servo gain control signal output to the RF AMP
30
SLCO
O
Motor Drive AMP signal output
31
SPDO
O
Motor Drive AMP signal output
32
TDO
O
Motor Drive AMP signal output
33
FDO
O
Motor Drive AMP signal output
34
DVDDO
—
Power supply terminal (+3.3V)
35
DVSS
—
Ground terminal
36
FG(PPI)
O
SPD FG signal output to the video DAC encoder
37
HIR0B
O
INT DET signal output to the video DAC encoder
38
HWAITB
O
RDY signal output to the video DAC encoder
39
HRESB
O
LSI RST signal output to the video DAC encoder
40
HRDB
O
RD signal output to the video DAC encoder
41
HWRB
O
WR signal output to the video DAC encoder
42
HCSB
O
SCD VD signal output to the video DAC encoder
43
HDATO
O
BEO1 signal output to the video DAC encoder
44
DVDD1
—
Power supply terminal (+3.3V)
45
DVSS
—
Ground terminal
46 to 52
HDAT1 to 7
I/O
Flash memory data bus
53 to 59
HADR0 to 6
O
Flash memory address bus
60
MWEB
O
S-RAM write enable signal output
MPEG BOARD  U707  LC78663N (AV DECODER)
52
HCD-SV2D
Pin No.
Pin Name
I/O
Description
61
MRAS1B
O
S-RAM low address strobe signal output
62 to 65
MA0 to 3
O
S-RAM address bus
66
DVDD3
—
Power supply terminal (+3.3V)
67
DVSS
—
Ground terminal
68 to 72
MA7 to 8
O
S-RAM address bus
73
MA9
—
Not used
74
MA10
—
Not used
75
MOEB
O
S-RAM output enable signal output
76
MCASUB
O
S-RAM column high address strobe signal output
77
MCASLB
O
S-RAM column low address strobe signal output
78 to 83
HADR7 to 12
O
Flash memory address bus
84
C2F
O
C2F signal output  to the video DAC encoder
85
ROMXA
O
CD DATA signal output video DAC encoder
86
ROMCK
O
BCK signal output video DAC encoder
87
LRSY
O
LRCK signal output to the video DAC encoder
88
DVDD1
—
Power supply terminal (+3.3V)
89
DVSS
—
Ground terminal
90
EMPH
—
Not used
91
AVRA01
O
DRFO signal output to the video DAC encoder
92
AVACK0
O
DACK signal output to the video DAC encoder
93
AVDACK
O
DACK signal output to the video DAC encoder
94
AVSCTB
O
DBGN signal output to the video DAC encoder
95
AVERRB
O
DFFR signal output to the video DAC encoder
96 to 103
AVD0 to 7
O
DVD (RF) signal output to the video DAC encoder
104
EFMOUT
—
Not used
105
PCK
—
Not used
106
DVDD0
—
Power supply terminal (+3.3V)
107
DVSS
—
Ground terminal
108
VCOCTL
I
FPD/PPD signal input
109
PPDO
O
PPD signal output
110
FPDO
O
FPD signal output
111
LF1
I
FPD/PPD signal input
112
LF2
I
FPD/PPD signal input
113
LF3
—
Not used
114
PCN
—
Not used
115
PISET
I
Not used in this set.   Fixed at “H”.
116
FISET
I
Not used in this set.   Fixed at “H”.
117
CDFR
I
Not used in this set.   Fixed at “L”.
118
DVDFR
I
Not used in this set.   Fixed at “L”.
119
AVDD2
—
Power supply terminal (+3.3V)
120
AVSS2
—
Ground terminal
121
DVCP1
I
Not used in this set.   Fixed at “H”.
122
JVCPC1
I
ADJV signal input
123
JVAO
O
ADJV signal output
124
JVAN
I
JVR signal input
125
JVRVO
O
JVR signal output
126
AVDD3
—
Power supply terminal (+3.3V)
127
AVSS
—
Ground terminal
128
VPDO
O
VPD signal output
Page of 72
Display

Click on the first or last page to see other CMT-SV2D / HCD-SV2D service manuals if exist.

RANDOM: