Sony CMT-SPZ55 / HCD-SPZ55 Service Manual ▷ View online
HCD-SPZ55
41
IC707 CXD9845M
/OTW 2
GVDD_B 1
PROTECTION
LOGIC
GATE
DRIVE
GVDD_A
36
BST_A
35
PVDD_A
34
OUT_A
33
GND
32
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
/SD 3
PWM_A 4
PWM_B 6
/RESET_AB 5
/RESET_CD 15
PWM_C 14
M1 13
M2 12
GND 11
GND 8
GND 9
GND 9
VREG 10
OC_ZDJ 7
PROTECTION
&
RESET LOGIC
OLP
OTP
OTP
CB3C
TIMING
CONTROL
STUCK
DETECT
STUCK
DETECT
STUCK
DETECT
REGULATOR
STUCK
DETECT
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GVDD_C
PWM_D 16
VDD 17
18
GATE
DRIVE
BST_C
27
PVDD_C
26
OUT_C
25
GND
24
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GATE
DRIVE
BST_B
28
PVDD_B
29
OUT_B
30
GND
31
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GATE
DRIVE
BST_D
20
GVDD_D
19
PVDD_D
21
OUT_D
22
GND
23
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROGRAMMABLE
CURRENT SENSE
CURRENT SENSE
TEMPERATURE
WARNING/ERROR
2
4
/HIZ_HS
4
/HIZ_LS
4
/OCH
4
/OCL
GVDD_D
GVDD_C
GVDD_B
GVDD_A
VREG
4
/RESET
VREG
UNDER
VOLTAGE
PROTECTION
POWER-UP
RESET
/UVP
GVDD_A
GVDD_D
GVDD_B
GVDD_C
VREG
HCD-SPZ55
42
– FL Board –
IC901 PT6315
– POWER Board –
IC601 MIP2F20MS1SO
5
OSC
OSC
DATA
SELECTOR
6
DOUT
7
DIN
8
CLK
9
STB
10
KEY1
11
KEY2
SERIAL
INTERFACE
DISPLAY MEMORY
24 BITS x 12 WORDS
24-BIT OUTPUT
LATCH
12-BIT SHIFT
REGISTER
SEGMENT
DRIVER
TIMING GENERATOR
KEY SCAN
COMMAND
DECODER
DIMMING
CIRCUIT
KEY DATA MEMORY
(2 x 16 BITS)
4-BIT LATCH
1
LED1
2
LED2
3
LED3
4
LED4
24
16
16
12
4
8
8
4
8
27 SEG14/KS14
29 SEG16/KS16
30 VEE
28 SEG15/KS15
8
31 SEG17/GRID12
33 SEG19/GRID10
32 SEG18/GRID11
32 SEG18/GRID11
23 SEG10/KS10
24 SEG11/KS11
25 SEG12/KS12
26 SEG13/KS13
22
SEG9/KS9
21
SEG8/KS8
20
SEG7/KS7
19
SEG6/KS6
18
SEG5/KS5
17
SEG4/KS4
16
SEG3/KS3
15
SEG2/KS2
14
SEG1/KS1
MULTIPLEXED
DRIVER
34
SEG20/GRID9
35
SEG21/GRID8
36
SEG22/GRID7
37
SEG23/GRID6
39
GRID4
40
GRID3
41
GRID2
42
GRID1
43
VDD
44
VSS
13
VDD
12
VSS
38
SEG24/GRID5
GRID
DRIVER
CONSTANT
CURRENT
SOURCE
2
FB
1
VDD
4
VCC
5 DRAIN
8 SOURCE
7 SOURCE
7 SOURCE
3
CL
VCL
CLAMP CIRCUIT
(ILIMIT SETTING)
IN
ICL.LOW
VCL.OUT
ILIMIT VARIABLE
CIRCUIT
+
–
–
+
–
+
–
–
7.2V
+
–
–
2.4V
VCC UV
VCC OVP
OVERHEAT
PROTECTION
S
R
R
Q
Q
Q
RESTARTING
TRIGGER
R
S
S
Q
Q
Q
+
–
–
27%
22%
22%
FOR LIGHT LOAD
DETECTION INTERMITTENT
OSCILLATION CONTROL
GENERATOR
CLOCK
12kHz
MAXDC
5.7V
5.0V
5.0V
VDD UV
5.7V
REGULATOR
VDD CLAMP
CIRCUIT
6.6V
+
–
ILIMIT
CORRECTION
CIRCUIT
FOR
DRAIN CURRENT
DETECT
GATE DRIVER
POWER
MOSFET
AT TURNING ON
BLANKING PULSE
GENERATION CIRCUIT
HCD-SPZ55
43
• IC Pin Function Description
CD BOARD IC201 CXD3014A-201R (CD DSP)
CD BOARD IC201 CXD3014A-201R (CD DSP)
Pin No.
Pin Name
I/O
Description
1
LRCK
O
L/R sampling clock signal output terminal
2
LRCKI
I
L/R sampling clock signal input terminal
3
PCMD
O
Serial data output terminal
4
PCMDI
I
Serial data input terminal
5
BCK
O
Bit clock signal output terminal
6
BCKI
I
Bit clock signal input terminal
7
XTACN
I
Oscillation circuit on/off control signal input from the system controller
"L": oscillation stop, "H": self-oscillation
"L": oscillation stop, "H": self-oscillation
8
XRST
I
System reset signal input from the system controller "L": reset
9
VSS
-
Ground terminal
10
IREQ-MP3
O
MP3 data request signal output to the system controller
11
CLOK
I
CD serial data transfer clock signal input from the system controller
12
DATA2
I
MP3 serial data input from the system controller
13
XLAT-MP3
I
MP3 serial data latch pulse signal input from the system controller
14
REQ-MP3
I
MP3 data request signal input from the system controller
15
ACK-MP3
O
MP3 acknowledge signal output to the system controller
16
XLAT
I
CD serial data latch pulse signal input from the system controller
17
VDD
-
Power supply terminal (+1.8V)
18
SVSS
-
Ground terminal
19
SVDD
-
Power supply terminal (+1.8V)
20
SENS
O
Internal status (SENSE) signal output to the system controller
21
WFCK
O
Write frame clock signal output terminal Not used
22
XUGF
O
XUGF signal output terminal Not used
23
XPCK
O
XPCK signal output terminal Not used
24
GFS
O
Guard frame sync signal output terminal Not used
25
C2PO
O
C2 pointer signal output terminal Not used
26
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
27
VDD
-
Power supply terminal (+1.8V)
28
COUT
O
Numbers of track counted signal output terminal Not used
29
SVSS
-
Ground terminal
30
SVDD
-
Power supply terminal (+1.8V)
31
MIRR
O
Mirror signal output terminal Not used
32
DFCT
O
Defect signal output terminal Not used
33
FOK
O
Focus OK signal output terminal Not used
34
VSS
-
Ground terminal
35
VDD
-
Power supply terminal (+1.8V)
36
VSS
-
Ground terminal
37
LOCK
O
GFS is sampled by 460 Hz "H" output when GFS is "H" Not used
38
MDP
O
Spindle motor servo control signal output terminal
39
SSTP
I
Disc inner position detection signal input terminal
40
IOVSS1
-
Ground terminal
41
SFDR
O
Sled servo drive signal (+) output terminal
42
SRDR
O
Sled servo drive signal (-) output terminal
43
TFDR
O
Tracking servo drive signal (+) output terminal
44
TRDR
O
Tracking servo drive signal (-) output terminal
45
FFDR
O
Focus servo drive signal (+) output terminal
46
FRDR
O
Focus servo drive signal (-) output terminal
47
IOVDD1
-
Power supply terminal (+3.3V)
48
AVDD0
-
Power supply terminal (+3.3V)
49
AVSS0
-
Ground terminal
50
E
I
E signal input from the optical pick-up block
51
F
I
F signal input from the optical pick-up block
52
TEI
I
Tracking error signal input terminal
53
TEO
O
Tracking error signal output terminal
54
FEI
I
Focus error signal input terminal
55
FEO
O
Focus error signal output terminal
56
VC
O
Middle point voltage output terminal
57
A
I
A signal input from the optical pick-up block
HCD-SPZ55
44
Pin No.
Pin Name
I/O
Description
58
B
I
B signal input from the optical pick-up block
59
C
I
C signal input from the optical pick-up block
60
D
I
D signal input from the optical pick-up block
61
AVDD4
-
Power supply terminal (+3.3V)
62
RFDCO
O
RFDC signal output terminal Not used
63
PDSENS
I
Reference voltage input terminal for PD
64
AC_SUM
O
RFAC summing amplifi er signal output terminal
65
EQ_IN
I
RF equalizer circuit input terminal
66
LD
O
Laser diode on/off control signal output to the automatic power control circuit
"H": laser diode on
"H": laser diode on
67
PD
I
Light amount monitor input from the laser diode of optical pick-up block
68
RFC
I
Equalizer cut off frequency adjustment terminal
69
AVSS4
-
Ground terminal
70
RFACO
O
EFM signal output terminal
71
RFACI
I
EFM signal input terminal
72
AVDD3
-
Power supply terminal (+3.3V)
73
BIAS
I
Asymmetry circuit constant current input terminal
74
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
75
ASYO
O
Playback EFM full-swing output terminal
76
VPCO
O
Charge pump output terminal for broad-band EFM PLL
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
AVSS3
-
Ground terminal
79
CLTV
I
VCO1 control voltage input terminal for multiplier
80
FILO
O
Filter output terminal for master PLL
81
FILI
I
Filter input terminal for master PLL
82
PCO
O
Charge pump output terminal for master PLL
83
SVSS
-
Ground terminal
84
SVDD
-
Power supply terminal (+1.8V)
85
SSTB-MP3
I
MP3 standby on/off control signal input terminal "L": standby Not used
86
VDD
-
Power supply terminal (+1.8V)
87
VSS
-
Ground terminal
88
TEST1
I
Input terminal for the test Normally: fi xed at "L"
89
DATA
I
CD serial data input from the system controller
90
CLK2
I
MP3 serial data transfer clock signal input from the system controller
91
SVSS
-
Ground terminal
92
SVDD
-
Power supply terminal (+2.5V)
93
JTAGTCK
I
Clock signal input terminal (for JTAG) Not used
94
JTAGTDI
I
Data input terminal (for JTAG) Not used
95
JTAGTDO
O
Data output terminal (for JTAG) Not used
96
JTAGTMS
I
Mode select signal input terminal (for JTAG) Not used
97
TRST
I
Reset signal input terminal (for JTAG) Not used
98
VSS
-
Ground terminal
99
VDD
-
Power supply terminal (+1.8V)
100
IOVDD2
-
Power supply terminal (+3.3V)
101
DOUT
O
Digital audio signal output terminal Not used
102
TEST
I
Input terminal for the test Normally: fi xed at "L"
103
TES1
I
Input terminal for the test Normally: fi xed at "L"
104
IOVSS2
-
Ground terminal
105
PLLVDD
-
Power supply terminal (+1.8V)
106
PLLVSS
-
Ground terminal
107
XVSS
-
Ground terminal
108
XTAO
O
System clock output terminal (16.9344 MHz)
109
XTAI
I
System clock input terminal (16.9344 MHz)
110
XVDD
-
Power supply terminal (+1.8V)
111
AVDD1
-
Power supply terminal (+3.3V)
112
AOUT1
O
L-ch analog audio signal output terminal
113
VREFL
O
L-ch reference voltage output terminal
114
AVSS1
-
Ground terminal
115
AVSS2
-
Ground terminal
116
VREFR
O
R-ch reference voltage output terminal
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