Sony CMT-EX1 / HCD-EX1 Service Manual ▷ View online
HCD-EX1
29
29
5-15. SCHEMATIC DIAGRAM – REG SECTION –
(Page 27)
(Page 23)
(Page 20)
HCD-EX1
30
30
5-16. IC BLOCK DIAGRAMS
• MAIN Board (1/3)
IC301 CXA2568M-T6
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP RF_EQ_AMP
ERROR AMP
FOCUS
FOCUS
TRACKING
ERROR AMP
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFO
RFE
FE
TE
(50%/30%
OFF)
OFF)
APC PD AMP
APC LD AMP
IC304 PCM1710U-B/1K
3
80
76
74
75
73
72
68
64 63
62 61
58
59
60
67 66 65
69
71 70
1
78
79
77
2
5
4
6
7
8
9
9
10
11
12
13
14
15
16
16
17
18
19
20
21 22
25 26 27 28 29 30 11 11
31 32
33 34
35 36 37
38 39 40
46
50
53
55
52
57
56
51
54
49
48
47
44
41
42
43
24
23
Clock
Generator
D/A
Interface
Error
Corrector
32K
RAM
Sub Code
Processor
EFM
demodurator
Digital
OUT
Digital
PLL
Asymmetry
Corrector
Servo
Auto
Sequencer
Digital
CLV
MIRR
DFCT
FOK
SERVO
Interface
CPU
Interface
OPAmp
Analog SW
A/D
Converter
PWM GENERATOR
FOCUS SERVO
SERVO DSP
SLED SERVO
TRACKING
SERVO
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
FORCUS PWM
GENERATOR
45
SIGNAL PROCESSOR BLOCK
SERVO BLOCK
MUTE
XRST
DVDD0
DATA
XLAT
CLOCK
SENS
SCLK
ATSK
WFCK
XUGF
XPCK
GFS
SCOR
WDCK
C4M
DVSS0
COUT
MIRR
V2PO
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FETO
DVDD1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DVSS1
TEST
TES1
VC
FE
SE
IGEN
AVSSO
ADIO
RFDC
CE
TE
TE
RFAC
ASYI
ASYO
AVDD0
AVDD0
AVDD1
AVSS1
BIAS
VCTL
V16M
VPCO
PCO
FILI
FILO
CLTV
EXCK
SBSO
SCSY
SQCK
SQSO
XOLT
SOCK
SOUT
XTAO
XTAI
DVSS2
XTSL
EMPH
BCK
PCMD
LRCK
DOUT
MD2
ASYE
DVDD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
28
INPUT
INTERFACE
DIGITAL
FILTER
NOISE
SHAPER
5-LEVEL DAC
RIGHT
LOW-PASS FILTER
RIGHT
3-STAGE AMP
RIGHT
LOW-PASS FILTER
LEFT
3-STAGE AMP
LEFT
5-LEVEL DAC
LEFT
MODE
CONTROL
TIMING
CONTROL
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
V
DD
V
CC
2R
GND2R
EXT1R
EXT2R
VOUTR
GND1
ML/DSD
MC/DM2
MD/DM1
MUTE
MODE
CKSL
DGND
V
DD
V
CC
2L
V
CC
1
GND2L
EXT1L
EXT2L
VOUTL
IC303 CXD2585Q
31
• LOADING Board
IC351 LB1641
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
32
5-17. IC PIN FUNCTIONS
• IC303 DIGITAL SERVO & DIGITAL SIGNAL PROCESSOR (CXA2585Q) (MAIN Board (1/3))
DVDD
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
CM4
WDCK
DVSS
COUT
MIRR
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FSTO
DVDD1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DVSS1
TEST
TES1
VC
FE
SE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
–
I
I
I
I
I
O
I
I/O
O
O
O
O
O
O
O
O
–
I/O
I/O
I/O
I/O
I
I/O
O
I
O
–
O
O
O
O
O
O
–
I
I
I
I
I
Digital power supply
System reset
“L” : reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Input pin for anti-shock (Connected to ground)
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
4.2336 MHz output (Not used)
Word clock output (ƒ = 2Fs)
Digital ground
Numbers of track counted signal input/output (Not used)
Mirror signal input/output
Defect signal input/output
Focus OK input/output
Spindle motor external control input (Connected to ground)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor servo
Input signal to detect disc inner most track
2/3 divider output of pin 71
Digital power supply
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Center voltage input pin
Focus error signal input
Sled error signal input
Pin No.
Pin Name
I/O
Function
• Abbreviation
GFS : Guarded Frame Sync
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