Sony CMT-EP505 / HCD-EP505 Service Manual ▷ View online
HCD-EP505
32
32
• IC Block Diagrams
– MAIN Board –
U401
LA1823 (EXCEPT AEP, UK, CH models)
U403
LC72131M-TL-M (AEP, UK, CH models)
Ver 1.1
U402
LA1837L (AEP, UK, CH models)
24
23
FM
RF
1
AM
RF
GND2
2
VCC2
REG
3
AM
MIX
AM
OSC
OSC
BUFFER
4
22
21
VCC1
20
FM
OSC
PHASE
COMP
FM
MIX
DECODER
5
6
19
GND1
7
MUTE
8
18
17
16
9
15
PILOT
DET
14
FM
DET
13
10
FM
S-METER
11
12
ST
ST SW
FF
VCO
FF
FF
TRIG
AM
IF
AM
DET
AGC
FM
IF
SD
IF
BUFFER
FMRF IN
RF GND
FMRF OUT
VCC2
FM OSC
DET OUT
MUTE
R
L
AM/FM
MO/ST
FM DET
AMRF IN
REG
AM OSC
VCC1
FM MIX
GND
FM BUFFER
AM OSC BUFFER
AM MIX
QUAD
AMIF
SD
ALC
BUFF
AM
OSC
AM
MIX
AM
RF. AMP
AGC
IF
DET
S-CURVE
AM/FM
IF-
BUFF
REG
TUNING
DRIVE
GND
VCC
PILOT
DET
VCO
FF
STEREO
DRIVE
STEREO
SW
MUTE
FF
FF
FM
IF
FM
DET
DECODER
ANT 1-BIRDIE
1
2 3
4
5
6
7
9
8
20
19
18
17 16
15
14
11
10
21
22
23
24
25
27
26
29
30
OSC.BUFF
FM-SD.ADJ
AM-OSC
REG
FM-AFC
AM-RF-IN
AGC
MPX-IN
FM-DET OUT
AM-DET OUT
OUT L
OUT R
AMP-IN L
AMP-IN R
AMP OUT R
AMP OUT L
VCO-STOP
STEREO
AM/FM
AM. SD
FM. SD
AM. SD ADJ
IF-BUFF
MUTE
VCC
FM DET
FM-IN
AM-MIX
FM-IF
AM-IF
GND
TUNED
S-METER
FM
S-METER
AM
COMP
SD
AM
12
13
PHASE
DET
28
PHASE
DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16, 1/17 4BITS
12BITS
PROGRAMMABLE
DRIVER
UNIVERSAL
COUNTER
REFERENCE
DIVIDER
POWER
ON
RESET
1/2
CCB
INTERFACE
1
2 3 4 5
6 7 8 9
16
15
14
13
12
11
10
17
18
19
20
XOUT
VSS
AOUT
AIN
PD
VDD
FMIN
AMIN
XIN
DO
CL
DI
CE
IFIN
IO1
BO4
BO3
BO2
BO1
IO2
UNLOCK
DETECTOR
DATA SHIFT REGISTER LATCH
U402
LC72131 (EXCEPT AEP, UK, CH models)
U501
LC75392
PHASE
DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16, 1/17 4BITS
12BITS
PROGRAMMABLE
DRIVER
UNIVERSAL
COUNTER
REFERENCE
DIVIDER
POWER
ON
RESET
1/2
CCB
INTERFACE
1
3 4 5 6
7 8 9 10
18
17
16
15
13
12
11
19
20
21
22
XOUT
VSS
AOUT
AIN
PD
VDD
FMIN
AMIN
14
NC
XIN
DO
CL
DI
CE
2
NC
IFIN
IO1
BO4
BO3
BO2
BO1
IO2
UNLOCK
DETECTOR
DATA SHIFT REGISTER LATCH
+
–
3
6
9
12
15
2
5
8
11
14
1
4
7
10
13
28
25
22
19
16
29
26
23
20
17
30
27
24
21
18
+
–
+
–
–
+
–
–
LATCH
DECODER
CONTROL
SHIFT
REGISTER
–
+
LVROUT
LVRIN
LTOUT
LTCOM
LT4
LT3
LT2
LT1
L4
L3
L2
L1
VDD
CL
DI
RVROUT
RVRIN
RTOUT
RTCOM
RT4
RT3
RT2
RT1
R4
R3
R2
R1
VREF
VSS
CE
U601
µ
PC1330HA
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
33
HCD-EP505
U603
BA335
– DISPLAY Board –
IC305
BU1924F-E2 (AEP, UK models)
U602
AN7312
RIPPLE FILTER
ALC
14
13
12
1
2
3
11
10
9
AMP. CH2
AMP. CH1
8
4
5
6
7
VCC
RF
ALC IN2
OUT2
PC2
NF2
IN2
GND
ALC CONST
ALC IN1
OUT1
PC1
NF1
IN1
AF AMP
COMPARATOR
1
2
3
4
5
6
7
8
9
V. N
C. R.
NF
NC
GND
TROUT
DIOUT
V8
VCC
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
Ver 1.1
34
HCD-EP505
6-18.
IC PIN FUNCTION DESCRIPTION
•
DISPLAY BOARD IC301
µ
PD780306GC-A68-8EU (SYSTEM CONTROLLER, LIQUID CRYSTAL DISPLAY DRIVER)
Pin No.
Pin Name
I/O
Description
1 to 4
KEY2 to KEY5
I
Key input terminal (A/D input)
5
ANALYZER
I
Analyzer level detection signal input terminal (A/D input) Not used
6
STATION
I
Tuning detection signal input terminal
7
RDSDATA
I
Serial data input from the RDS decoder (Used for the AEP, UK models)
8
AVDD
—
Power supply terminal
9
AVREF
I
Reference voltage input terminal
10, 11
CDOUT1, CDOUT2
O
Not used
12
VSS
—
Ground terminal
13
TIME
O
LED drive signal output terminal
14
CDDATA
I/O
Two-way data bus with the CD block
15
CDRESET
O
Reset signal output to the CD block “L”: reset
16
REC-EN
O
REC bias control signal output terminal
17
INPINENA
O
Mega bass on/off selection signal output terminal “H”: mega bass on
18
REC-LED
O
LED drive signal output terminal
19
SOUNDENA
O
chip enable signal output foe the LC75392
20
PLLENA
O
PLL chip enable signal output to the FM/AM PLL “H” active
21
MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
22
POWER
O
System power on/off control signal output terminal “H”: power on
23 to 26
COM0 to COM3
O
Common drive signal output to the liquid crystal display
27
BIAS
O
Bias output for the liquid crystal display drive
28 to 30
VLC0 to VLC2
I
Input terminal for doubler circuit capacitor connection to develop liquid crystal display drive
voltage
voltage
31
VSS
—
Ground terminal
32 to 61
SEG0 to SEG29
O
Segment drive signal output to the liquid crystal display
62
SEG30
I/O
Segment drive signal output to the liquid crystal display
AM frequency select switch input terminal
(AM frequency select switch: used for the except AEP, UK, chinese models)
AM frequency select switch input terminal
(AM frequency select switch: used for the except AEP, UK, chinese models)
63
SEG31
I/O
Segment drive signal output to the liquid crystal display
AM frequency select switch input terminal
(AM frequency select switch: used for the except AEP, UK, chinese models)
AM frequency select switch input terminal
(AM frequency select switch: used for the except AEP, UK, chinese models)
64
SEG32
Segment drive signal output to the liquid crystal display
65
SEG33
O
Segment drive signal output to the liquid crystal display Not used
66
SEL10
I
Head position detect switch input terminal “L”: reverse direction, “H”: forward direction
67
SEG35
O
Segment drive signal output to the liquid crystal display Not used
68
SEL12
I
Cassette tape detect switch input terminal “L”: no cassette, “H”: cassette in
69
SEG37
O
Segment drive signal output to the liquid crystal display Not used
70
SEL14
I
Rec-proof claw (forward direction) detection signal input from the protect detect switch
“L”: recording possible, “H”: protect
“L”: recording possible, “H”: protect
71
SEL15
I
Rec-proof claw (reverse direction) detection signal input from the protect detect switch
“L”: recording possible, “H”: protect
“L”: recording possible, “H”: protect
72
DATAIN
I
Serial data input from the FM/AM PLL
73
DATAOUT
O
Serial data output to the FM/AM PLL and LC75392
74
CLK
O
Serial data transfer clock signal output to the FM/AM PLL and LC75392
75
EEPROMDATA
I/O
Two-way data bus with the EEPROM
76
STEREO
I
FM stereo detection signal input terminal “L”: stereo
77
EEPROMCLK
O
Clock signal output to the EEPROM
Ver 1.1
35
HCD-EP505
Pin No.
Pin Name
I/O
Description
78
VSS
—
Ground terminal
79
X2
O
Main system clock output terminal (4.194304 MHz)
80
X1
I
Main system clock input terminal (4.194304 MHz)
81
VDD
—
Power supply terminal
82
XT1
I
Sub system clock input terminal (32.768 kHz) Not used
83
XT2
O
Sub system clock output terminal (32.768 kHz) Not used
84
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
85
REMOTE
I
Remote control signal input from the remote control receiver
86
PWRFAIL
I
Power failure detection signal input terminal “L”: power failure, “H”: power on
87
RDSCLK
I
Serial data transfer clock signal input from the RDS decoder
(Used for the AEP, UK models)
(Used for the AEP, UK models)
88
CDCLK
I
Serial data transfer clock signal input from the CD block
89
SENSORB
I
Tape sensor input terminal Not used
90
SENSORA
I
Tape play/rec detect sensor input terminal “L” input when the tape play/rec detect
91
CD DOOR SW
I
CD lid open/close detect switch (SW300) input terminal “L”: CD lid is closed
92
CD-EN
O
CD power on/off control signal output terminal
93
SOL
O
Trigger plunger drive signal output terminal “H”: trigger plunger on
94
TU-EN
O
Tuner power on/off control signal output terminal
95
MOTOR-ON
O
Motor control signal output terminal
96
AMS
I
Whether a music is present or not from AMS is detected at auto music sensor
“L”: music is not present, “H”: music is present
“L”: music is not present, “H”: music is present
97
ENCODERA
I
Jog dial pulse input from the rotary encoder (VOLUME) (A phase input)
98
ENCODERB
I
Jog dial pulse input from the rotary encoder (VOLUME) (B phase input)
99
AVSS
—
Ground terminal
100
KEY1
I
Key input terminal (A/D input)
Ver 1.1
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