Sony CMT-DC1K / HCD-DC1K Service Manual ▷ View online
HCD-DC1K
30
30
POWER BOARD
2
(AC IN)
SUB POWER
TRANSFORMER
MAIN POWER
TRANSFORMER
*
*
NOT REPLACEABLE:
BUILT IN TRANSFORMER.
BUILT IN TRANSFORMER.
1-682-413-
11
(11)
MAIN BOARD
CNP101
G
JW920
JW921
JW912
JW913
A
B
C
D
E
F
G
1
2
3
4
5
6
6-15. PRINTED WIRING BOARD – POWER Board –
•
See page 18 for Circuit Boards Location.
• Semiconductor
Location
Ref. No.
Location
(Page 27)
D902
G-5
D903
F-5
D904
G-5
D905
F-5
D906
C-5
D907
C-4
D908
C-5
D909
C-4
D910
B-3
D911
B-3
D912
B-3
D913
B-3
D915
A-4
D917
A-5
D918
C-4
Q901
A-5
Q902
B-4
HCD-DC1K
31
31
6-16. SCHEMATIC DIAGRAM – POWER Board –
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
no mark : FM
(Page 25)
The components identified by mark
0
or dotted
line with mark
0
are critical for safety.
Replace only with part number specified.
HCD-DC1K
32
32
6-17.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC801 CXP83124A-050Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
TAPE-END
I
Tape end detect sensor input terminal “H”: input when the tape end detected
2
RDS-IN
I
Serial data reading clock signal input from the RDS decoder Not used (open)
3
REMOCON
I
SIRCS remote control signal input from the remote control receiver (IC802)
4
MOT-CON
O
Capstan/reel motor on/off control signal output terminal “H”: motor on
5
C-DATA/
TU-DATA
O
Serial data output to the DSP/SSP (IC101) (at CD function)
PLL serial data output to the tuner pack (at tuner function)
PLL serial data output to the tuner pack (at tuner function)
6
T-MODE
I
Head position detect switch input terminal “L”: forward direction, “H”: reverse direction
7
REG-CON
O
Main system power supply on/off contorl signal output terminal “H”: power on
8
C-CLK/TU-CLK
O
Serial data transfer clock signal output to the DSP/SSP (IC101) (at CD function)
PLL serial data transfer clock signal output to the tuner pack (at tuner funcion)
PLL serial data transfer clock signal output to the tuner pack (at tuner funcion)
9
JOG-C (BASS)
I
Jog dial pulse input from the rotary encoder (C phase input) Not used (fixed at “L”)
10
SOL-CON
O
Trigger plunger on/off control signal output terminal “H”: plunger on
11
C-SQCK
O
Subcode Q data reading clock signal output ti the DSP (IC110) (at CD function)
12
C-SQSO/
RDS-DATA
I
Subcode Q data input from the DSP (IC101) (at CD function)
RDS serial data input from the RDS decoder (not used) (at tuner function)
RDS serial data input from the RDS decoder (not used) (at tuner function)
13
TRAY-OPEN
O
Motor drive siganl output to the disc tray open/close motor driver (IC320) “H”: active
14
HOLD
O
Automatic power control hold signal output to the RF Amp (IC103)
15
TRAY-CLOSE
O
Motor drive signal output to the disc tray open/close motor driver (IC309) “H”: active
16
JOG-D (BASS)
I
Jog dial pulse input from the rotary encoder (D phase input) Not used (fixed at “L”)
17
TUNED
I
Tuning detection signal input from the LA1837M (IC1) (at tuner function)
18
SENSE2/
TU-COUNT
I
Internal status detection monitor input from the DSP (IC101) (for MIRR, DFCT2, etc.) (at CD
function)
PLL count data input from the tuner pack (at tuner function)
function)
PLL count data input from the tuner pack (at tuner function)
19
C-LATCH/
TU-CE
O
Serial data latch pulse output to the DSP (IC101) (at CD function)
PLL serial chip enable signal output to the tuner pack (at tuner function)
PLL serial chip enable signal output to the tuner pack (at tuner function)
20
JOG-B
I
Jog dial pulse input from the rotary encoder (RV801 VOLUME) (B phase input)
21
JOG-A
I
Jog dial pulse input from the rotary encoder (RV801 VOLUME) (A phase input)
22
AMP-MUTE
O
Muting on/off control signal output to the power amplifier (IC101, 201) “H”: muting on
23
JOG-G
I
Jog dial pulse input from the rotary encoder (G phase input) Not used (fixed at “L”)
24
HP-CHK
I
Headphone jack in/out check detection signal input terminal
25
TU-ON
O
Power supply on/off control signal output of the tuner section (FM +7.5V)
LED drive signal output of the TUNER/BAND indicator (D853)
“H”: tuner power on (LED on)
LED drive signal output of the TUNER/BAND indicator (D853)
“H”: tuner power on (LED on)
26
D. S. G.
O
LED drive signal output of the DSG (Dynamic Sound Generator) indicator (D854)
“H”: LED on
“H”: LED on
27
CD-SYNC
O
LED drive signal output of the CD SYNC indicator (D856) “H”: LED on
28
SCK
O
Serial data transfer clock signal output to the BD3861FS (IC323)
29
JOG-E
I
Jog dial pulse input from the rotary encoder (E phase input) Not used (fixed at “L”)
30
JOG-F
I
Jog dial pulse input from the rotary encoder (F phase input) Not used (fixed at “L”)
31
JOG-H
I
Jog dial pulse input from the rotary encoder (H phase input) Not used (fixed at “L”)
32
TC-SW
I
Half detect (side A and B) switch and cassette in detect switch input terminal (A/D input)
33
TRAY-SW
I
Disc tray position detect switch (S1) input terminal (A/D input)
“L”: close position, “M”: open position, “H”: moving
“L”: close position, “M”: open position, “H”: moving
34
KEY3
I
Key input terminal (A/D input) S813 to S816 (TUNER/BAND, TUNING +/–, FUNCTION
input)
input)
35
KEY2
I
Key input terminal (A/D input) S801 to S806 (I/1, CD u/x/M/m/Z keys input)
36
KEY1
I
Key input terminal (A/D input)
S807 to S812 (TAPE n N/x/M/m/X, CD SYNC keys input)
S807 to S812 (TAPE n N/x/M/m/X, CD SYNC keys input)
Pin No.
Pin Name
I/O
Description
37
SIMUKE/TEST
I
Destination setting terminal (A/D input)
38
RESET
I
System reset signal input from the reset signal generator (IC803) “L”: reset
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”
39
EXTAL1
O
Main system clock input terminal (4.19MHz)
40
XTAL1
O
Main system clock output terminal (4.19MHz)
41
VSS
—
Ground terminal
42
XTAL2
O
Sub system clock output terminal (500kHz) Not used (open)
43
EXTAL2
I
Sub system clock input terminal (500kHz) Not used (fixed at “L”)
44
AVREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
45
AVSS
—
Ground terminal (for A/D conversion)
46
VL
O
Liquid crystal display bias on/off control signal output terminal
47 to 49
VLC3 to VLC1
—
Power supply terminal for the liquid crystal display bias
50 to 53
COM0 to COM3
O
Common drive signal output to the liquid crystal display (LCD801)
54 to 85
SEG0 to SEG31
O
Segment drive signal output to the liquid crystal display (LCD801)
86
C-XRST/FM ON
O
Reset signal output to the DSP (IC101) and BA5974FP (IC102) (at CD function)
FM power supply ON/OFF control signal output to the tuner section (FM +7.5V
(at tuner function)
FM power supply ON/OFF control signal output to the tuner section (FM +7.5V
(at tuner function)
87
REC-MUTE
O
Recording muting on/off selection signal output to the Tape section “H”: muting on
88
SDA
O
Serial data output to the BD861FS (IC323)
89
VDD
—
Power supply terminal (+5V)
90
NC
—
Not used (open)
91
VSS
—
Ground terminal
92
TX
O
Sub system clock output terminal (32.768kHz)
93
TEX
I
Sub system clock input terminal (32.768kHz)
94
CD-ON
O
Power supply on/off control signal output of the CD section (+5V)
LED drive signal output of the CD u indicator (D852) “H”: CD power on (LED on)
LED drive signal output of the CD u indicator (D852) “H”: CD power on (LED on)
95
REC/PB
O
Recording/playback selection signal output to the BA3126N (IC402)
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
96
L-MUTE
O
Line muting on/off selection signal output to the Tape section “H”: muting on
97
AU-MUTE
O
Muting on/off control signal output terminal “H”: muting on
98
TC-ON
O
Power supply on/off control signal output of the cassette holder back light
LED drive signal output of the TAPE n N indicator (D855) “H”: back light on (LED on)
LED drive signal output of the TAPE n N indicator (D855) “H”: back light on (LED on)
99
WP
I
Wakeup control signal input terminal
100
C-SCOR
I
Subcode sync (S0+S1) detection signal input from DSP on the CD section (at CD function)
33
HCD-DC1K
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTION
CORRECTION
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
• IC Block Diagrams
– CD Board –
– CD Board –
IC101
CXD2587Q
IC102
BA5974FP-E2
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