Sony CMT-CPX1 / HCD-CPX1 Service Manual ▷ View online
41
HCD-CPX1
IC603
PCM1802DBR
SINGLE-END/
DIFFERENTIAL
CONVERTER
5TH ORDER
DELTA-SIGMA
MODULATOR
VINL
1
SINGLE-END/
DIFFERENTIAL
CONVERTER
VINR
2
VREF1
3
VREF2
4
5TH ORDER
DELTA-SIGMA
MODULATOR
REFERENCE
x16 1/64
(x1/128)
DECIMATION
FILTER
WITH
DC CUT
FILTER
SERIAL
INTERFACE
&
MODE/FORMAT
CONTROL
MODE1
20
MODE0
19
FMT1
18
FMT0
17
DOUT
12
BCK
11
OSR
16
SCKI
15
VDD
14
DGND
13
CLOCK & TIMING CONTROL
PDWN
7
BYPAS
8
VCC
5
AGND
6
FSYNC
9
LRCK 10
POWER
SUPPLY
– LCD Board –
IC803
BU9728AKS
2
3
6
7
8
9
10
11
12
TIMING
GENERATOR
LCD DRIVER
BIAS CIRCUIT
COMMON
COUNTER
COUNTER
4
5
SERIAL
INTERFACE
ADDRESS
COUNTER
COUNTER
COMMAND/DATA
REGISTER
COMMAND
DECODER
DISPLAY DATA RAM
(DD RAM)
LCD
SEGMENT
DRIVER
32BITS
55 – 44
20 – 27
OSC1
1
N.C.
OSC2
V1
V2
V3
VSS
VDD
SCK
SD
CS
C/D
19
RESET
SEG31
ı
SEG2
0
SEG0
ı
SEG7
SEG19
ı
SEG8
17
16
18
COM3
COM2
COM1
15
N.C
28
N.C
13
COM0
14
N.C
41
ı
30
LCD COMMON
DRIVER 4BITS
DRIVER 4BITS
29
N.C
42
N.C
43
N.C
56
N.C
42
HCD-CPX1
•
MAIN BOARD IC401 M30622MGN-B08FP (SYSTEM CONTROLLER (CD MECHANISM CONTROL))
Pin No.
Pin Name
I/O
Description
1
LCD ON
O
Power on/off control signal output for liquid crystal display “H”: power on
2
RDS DATA
I
Serial data input from the RDS decoder on the tuner unit
3
LCD CD
O
Signal output for discriminating between command and display data to the liquid crystal display
driver “L”: display data, “H”: command
driver “L”: display data, “H”: command
4
SIRCS IN/WAKE
I
Remote control signal input terminal
5
LCD DATA
O
Serial data output to the liquid crystal display driver
6
LCD CS
O
Chip select signal output to the liquid crystal display driver “L” active
7
LCD CLK
O
Serial data transfer clock signal output to the liquid crystal display driver
8
BYTE
—
Not used
9
CNVSS
—
Ground terminal
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Not used
18
RDS CLK
I
Serial data transfer clock signal input from the RDS decoder on the tuner unit
19
CD SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal generator “L”: AC cut checked
21
ST MUTE
O
Tuner muting on/off control signal output to the tuner unit “H”: muting on
22
ST CE
O
PLL chip enable signal output to the tuner unit
23
ST DATA OUT
O
PLL serial data output to the tuner unit
24
CD PWM3
O
RFDC PWM signal output to the RF amplifier
25
ST DATA IN
I
PLL serial data input from the tuner unit
26
CD PWM2
O
PWM signal output to the RF amplifier
27
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
28
CD PWM1
O
Focus servo drive PWM signal output to the RF amplifier
29
IIC CLK
I/O
Communication data transfer clock signal input/output terminal Not used
30
IIC DATA
I/O
Communication data bus terminal Not used
31
NO USE
—
Not used
32
CD SQSO
I
Subcode Q data input from the digital signal processor
33
CD SQCLK
O
Subcode Q data reading clock signal output to the digital signal processor
34
ST STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
35
CD DATA
O
Serial data output to the digital signal processor
36
CD XLT
O
Serial data latch pulse signal output to the digital signal processor
37
CD CLK
O
Serial data transfer clock signal output to the digital signal processor
38
TC PLAY SW
I
Head position detect switch input terminal
39
32K OUT
O
Clock (32.768 kHz) signal output terminal Not used
40
TC LINE MUTE
O
Line muting on/off control signal output to the recording/playback equalizer amplifier
“H”: muting on
“H”: muting on
41
TC REC/MUTE
O
Recording muting on/off control signal output to the recording/playback equalizer amplifier
“L”: muting on
“L”: muting on
42
TC BIAS-ON
O
Recording bias on/off control signal output terminal “H”: bias on
43
TC PB/REC
O
Recording/playback selection signal output terminal “L”: playback, “H”: recording
6-19.
IC PIN FUNCTION DESCRIPTION
43
HCD-CPX1
Pin No.
Pin Name
I/O
Description
44
LED STANDBY
O
LED drive signal output of the standby indicator “H”: LED on
45
SC DT
O
Serial data output to the digital audio signal processor
46
SC SHIFT
O
Serial data shift clock signal output to the digital audio signal processor
47
SC LATCH
O
Serial data latch pulse signal output to the digital audio signal processor
48
NSP MUTE
O
Muting on/off control signal output to the digital audio signal processor “L”: muting on
49
INIT
O
Reset signal output to the digital audio signal processor “L”: reset
50
HP DET
I
Headphone jack connection detection signal input terminal
“L”: no connected, “H”: headphone connected
“L”: no connected, “H”: headphone connected
51
LED BL
O
Power on/off control signal output for the liquid crystal display back light “H”: power on
52
VOL B
I
Jog dial pulse input from the rotary encoder (VOLUME) (B phase input)
53
VOL A
I
Jog dial pulse input from the rotary encoder (VOLUME) (A phase input)
54
CD LD-ON
O
CD-ROM/RW selection signal output to the RF amplifier “L”: CD-ROM, “H”: CD-RW
55
ENA
O
Output enable control signal output to the power amplifier
56
CD SENS
I
Internal status detection monitor input from the digital signal processor
57
ST TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
58
TC TRG
O
Trigger plunger on/off control signal output terminal “H”: plunger on
59
TC CAPM-CONT
O
Capstan/reel motor on/off control signal output terminal “H”: motor on
60
CD XRST
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
61
DIAG
I
Protect signal input from the power amplifier and protect detect circuit
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT TEST
O
Output terminal for the software test Not used
64
VSS
—
Ground terminal
65
CD BD-PWR
O
Power supply on/off control signal output for the CD section “H”: power on
66
SP RELAY
O
Relay drive signal output for the speaker protect Not used
67
CDM LOAD-OUT
O
Motor drive signal (open direction) output terminal
68
CDM LOAD-IN
O
Motor drive signal (close direction) output terminal
69
CDM OUT-SW
I
Loading in/out detect switch input terminal “L”: loading out
70
CDM IN-SW
I
Loading in/out detect switch input terminal “L”: loading in
71
BASS A
I
Jog dial pulse input from the rotary encoder (BASS) (A phase input)
72
BASS B
I
Jog dial pulse input from the rotary encoder (BASS) (B phase input)
73
P DOWN
O
Power down control signal output to the A/D converter “L”: power down
74
KEY WAKE UP
I
System wake up signal input by pressing any key
75
—
—
Not used
76
TRE A
I
Jog dial pulse input from the rotary encoder (TREBLE) (A phase input)
77
TRE B
I
Jog dial pulse input from the rotary encoder (TREBLE) (B phase input)
78
CD MUTE
O
CD analog signal muting on/off control signal output terminal “H”: muting on
79
LED CD
O
LED drive signal output of the CD NX indicator “H”: LED on
80
TC ALC
O
Automatic limiter control signal output to the recording/playback equalizer amplifier
“H”: limiter on
“H”: limiter on
81
LINE MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
82
PWR RELAY
O
Main system power supply on/off control signal output terminal “H”: power on
83
LED DSG
O
LED drive signal output of the DSG indicator “H”: LED on
84
LED TUNER
O
LED drive signal output of the TUNER BAND indicator “H”: LED on
85
HP MUTE
O
Headphone muting on/off control signal output terminal “H”: muting on
86
EQ CE
O
Chip enable signal output to the electrical volume
87
EQ DATA
O
Serial data output to the electrical volume
88
EQ CLK
O
Serial data transfer clock signal output to the electrical volume
89
LED TC
O
LED drive signal output of the TAPE nN indicator “H”: LED on
44
HCD-CPX1
Pin No.
Pin Name
I/O
Description
90
TC END SW
I
Tape end detect switch input terminal
91
TC HALF/REC/SW
I
Recording-proof claw (forward/reverse) detect switch and cassette in detect switch input terminal
(A/D input)
(A/D input)
92
MODEL
I
Model setting terminal
93
DEST
I
Destination setting terminal
94, 95
KEY3, KEY2
I
Front panel key input terminal (A/D input)
96
AVSS
—
Ground terminal (for analog system)
97
KEY1
I
Front panel key input terminal (A/D input)
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVCC
—
Power supply terminal (+3.3V) (for analog system)
100
LCD RESET
O
Reset signal output to the liquid crystal display driver “L”: reset
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