Sony CMT-CPX1 / HCD-CPX1 (serv.man2) Service Manual ▷ View online
41
HCD-CPX1
– MAIN Board –
IC101
LC75342
30
29
1
2
CCB
INTERFACE
CONTROL
CIRCUIT
LOGIC
CIRCUIT
CONTROL
CIRCUIT
26
+
–
25
24
+
–
23 22 21
20 19 18 17
+
–
+
–
–
5
+
–
–
6
7
+
–
–
8
9
10
11 12 13 14
+
–
–
+
–
3
LOUT
LBASS2
LBASS1
LTRE
LIN
LSELO
L4
L3
L2
L1
15
NC
VSS
4
TEST
VDD
ROUT
RBASS2
RBASS1
RTRE
RIN
RSELO
R4
R3
R2
R1
16
NC
CL
DI
CE
28
+
–
RVREF
+
–
LVREF
VREF
27
NC
IC201
BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
O
UT2
O
UT1
RNF
VM
VCC
FIN
GND
RIN
– AMP Board –
IC600
CXD9743N
PWM
CLOCK
GENERATOR
(SECONDARY)
17 18 19 20 21
BCK
16
LRCK
DATA
BFVDD
BFVSS
XFSIIN
15
INIT
14
NSPMUTE
13
SCLATCH
12
SCSHIFT
11
SCDT
10
MCKSEL
4
OUTL2
5
XOVDD
3
VSSL
8
DVDD
9
DVSS
7
XOVSS
2
OUTL1
1
VDDL
CLOCK
GENERATOR
(PRIMARY)
S g P
RATE
CONVERTER
DF1
DF2
GAIN
CONTROL
LINER
INTERPOLATOR
(2 TIMES)
∆∑
INIT/
MUTE
SERIAL
CONTROL
6
XFSOOUT
22
FSOCKO
41
OUTR1
40
VSSR
39
OUTR2
38
VSUBC
42
VDDR
36
XFSOIN
35
XVSS
34
HPVDDL
33
HPOUTL1
37
XVDD
31
HPOUTL2
30
HPVDDR
29
HPOUTR1
27
HPOUTR2
28
HPVSSR
32
HPVSSL
23
FSOI
24
SFLAGO
25
TEST2
26
TEST1
42
HCD-CPX1
IC618
NJM2870F18 (TE2)
5
VIN
4
VOU
T
2
GND
3
NOISE
BYPASS
1
CONTROL
BANDGAP
REFERENCE
THERMAL
PROTECTION
IC650, 680
CXD9750L
CROSS OVER
DELAY
FILTER
THERMAL
SHUT DOWN
UNDER
VOLTAGE
LOCK–OUT
HIGH SIDE
LEVEL SHIFT
PROTECTOR
CIRCUIT
PRE
DRIVER
LOW SIDE
LEVEL SHIFT
PRE
DRIVER
-
16
INB
15
GNDB
14
VDDB
20
SB
19
OUTB
13
VDRVB
12
VBOOTB
11
VBBB
VDRVB
VBBB
17
ENB
18
DIAGB
CROSS OVER
DELAY
THERMAL
SHUT DOWN
UNDER
VOLTAGE
LOCK–OUT
HIGH SIDE
LEVEL SHIFT
PROTECTOR
CIRCUIT
PRE
DRIVER
LOW SIDE
LEVEL SHIFT
PRE
DRIVER
6
INA
5
GNDA
4
VDDA
10
SA
9
OUTA
3
VDRVA
2
VBOOTA
1
VBBA
VDRVA
VBBA
7
ENA
8
DIAGA
VDRVA
VDRVB
VBBA
VBBB
VBBB
+
FILTER
+
-
-
VBBA
+
+ -
43
HCD-CPX1
IC603
PCM1802DBR
SINGLE-END/
DIFFERENTIAL
CONVERTER
5TH ORDER
DELTA-SIGMA
MODULATOR
VINL
1
SINGLE-END/
DIFFERENTIAL
CONVERTER
VINR
2
VREF1
3
VREF2
4
5TH ORDER
DELTA-SIGMA
MODULATOR
REFERENCE
x16 1/64
(x1/128)
DECIMATION
FILTER
WITH
DC CUT
FILTER
SERIAL
INTERFACE
&
MODE/FORMAT
CONTROL
MODE1
20
MODE0
19
FMT1
18
FMT0
17
DOUT
12
BCK
11
OSR
16
SCKI
15
VDD
14
DGND
13
CLOCK & TIMING CONTROL
PDWN
7
BYPAS
8
VCC
5
AGND
6
FSYNC
9
LRCK 10
POWER
SUPPLY
– LCD Board –
IC803
BU9728AKS
2
3
6
7
8
9
10
11
12
TIMING
GENERATOR
LCD DRIVER
BIAS CIRCUIT
COMMON
COUNTER
COUNTER
4
5
SERIAL
INTERFACE
ADDRESS
COUNTER
COUNTER
COMMAND/DATA
REGISTER
COMMAND
DECODER
DISPLAY DATA RAM
(DD RAM)
LCD
SEGMENT
DRIVER
32BITS
55 – 44
20 – 27
OSC1
1
N.C.
OSC2
V1
V2
V3
VSS
VDD
SCK
SD
CS
C/D
19
RESET
SEG31
ı
SEG2
0
SEG0
ı
SEG7
SEG19
ı
SEG8
17
16
18
COM3
COM2
COM1
15
N.C
28
N.C
13
COM0
14
N.C
41
ı
30
LCD COMMON
DRIVER 4BITS
DRIVER 4BITS
29
N.C
42
N.C
43
N.C
56
N.C
44
HCD-CPX1
6-19.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC401 M30622MGN-B08FP (SYSTEM CONTROLLER (CD MECHANISM CONTROL))
Pin No.
Pin Name
I/O
Description
1
LCD ON
O
Power on/off control signal output for liquid crystal display “H”: power on
2
RDS DATA
I
Serial data input from the RDS decoder Not used
3
LCD CD
O
Signal output for discriminating between command and display data to the liquid crystal display
driver “L”: display data, “H”: command
driver “L”: display data, “H”: command
4
SIRCS IN/WAKE
I
Remote control signal input terminal
5
LCD DATA
O
Serial data output to the liquid crystal display driver
6
LCD CS
O
Chip select signal output to the liquid crystal display driver “L” active
7
LCD CLK
O
Serial data transfer clock signal output to the liquid crystal display driver
8
BYTE
—
Not used
9
CNVSS
—
Ground terminal
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Not used
18
RDS CLK
I
Serial data transfer clock signal input from the RDS decoder Not used
19
CD SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal generator “L”: AC cut checked
21
ST MUTE
O
Tuner muting on/off control signal output to the tuner unit “H”: muting on
22
ST CE
O
PLL chip enable signal output to the tuner unit
23
ST DATA OUT
O
PLL serial data output to the tuner unit
24
CD PWM3
O
RFDC PWM signal output to the RF amplifier
25
ST DATA IN
I
PLL serial data input from the tuner unit
26
CD PWM2
O
PWM signal output to the RF amplifier
27
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
28
CD PWM1
O
Focus servo drive PWM signal output to the RF amplifier
29
IIC CLK
I/O
Communication data transfer clock signal input/output terminal Not used
30
IIC DATA
I/O
Communication data bus terminal Not used
31
NO USE
—
Not used
32
CD SQSO
I
Subcode Q data input from the digital signal processor
33
CD SQCLK
O
Subcode Q data reading clock signal output to the digital signal processor
34
ST STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
35
CD DATA
O
Serial data output to the digital signal processor
36
CD XLT
O
Serial data latch pulse signal output to the digital signal processor
37
CD CLK
O
Serial data transfer clock signal output to the digital signal processor
38
TC PLAY SW
I
Head position detect switch input terminal
39
32K OUT
O
Clock (32.768 kHz) signal output terminal Not used
40
TC LINE MUTE
O
Line muting on/off control signal output to the recording/playback equalizer amplifier
“H”: muting on
“H”: muting on
41
TC REC/MUTE
O
Recording muting on/off control signal output to the recording/playback equalizer amplifier
“L”: muting on
“L”: muting on
42
TC BIAS-ON
O
Recording bias on/off control signal output terminal “H”: bias on
43
TC PB/REC
O
Recording/playback selection signal output terminal “L”: playback, “H”: recording
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