Sony CMT-CP500MD / HCD-CP500MD Service Manual ▷ View online
61
HCD-CP500MD
7-19.
IC BLOCK DIAGRAMS
IC101, 201 TDA7296
IC307 KA3082
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–VS
STBY
MUTE
NC
NC
+PWVS
OUT
–PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
CH2/A CH2/B
NF
VCC
CG
NF
ALC
METAL
OUT
PRE
OUT
OUT
TAPE A
/TAPE B
REC
OUT
OUT
REC
IN
CH1/A CH1/B
NF
GND1
M/H
NF
CH2
CH2
ALC
M/N
CH1
GND
GND
CH1
+
–
+
–
+
–
+
–
A/B
GND
METAL
OUT
PRE
OUT
OUT
MIX
OUT
REC
OUT
OUT
REC
IN
IREF
VREF2
VREF1
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
IC401 TA8189N
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
IC308 M62016L
IC309 BU1924F
5
6
7
8
4
3
2
1
12
11
10
9
13
14
15
16
QUAL
RD
ATA
VREF
MUX
VDD1
VSS1
VSS3
CMP
T2
T1
VSS2
VDD2
XI
XO
(NC)
RCLK
8TH SWITCHED
CAPACITOR FILTER
COMPARATOR
PLL
57kHz
RDS/ARI
PLL
1187.5Hz
BI-PHASE
DECODER
DECODER
DIFFERENTIAL
DECODER
TEST
CLOCK
DIGITAL
ANALOG
ANTI-ALIASING
FILTER
62
HCD-CP500MD
IC1004 BA6209N
MOTOR
DRIVE
FORWARD
/REVERSE
CONTROL
MOTOR
DRIVE
1 2
3
4
5
6
7 8 9
10
GND
OUT1
VZ1
VR
FIN
RIN
VCC1
VCC2
VZ2
OUT2
IC1005
µ
DA1360TS
IC1006
µ
DA1350AH
3
2
1
15
16
VINR
4
VREF (N)
5
VREF (P)
6
SFOR
7
PWON
8
SYSCLK
VREF
VINL
VSSA
14 FSEL
13 DATAO
12 WS
11 BCK
10 VSSD
9 VDDD
VDDA
+
–
+
–
ADC
( )
ADC
( )
DECIMATION
FILTER
DIGITAL
INTERFACE
DC-
CANCELLATION
FILTER
CLOCK
CONTROL
3
2
1
32
33
VSSD
4
VSSD (C)
5
L3DATA
6
L3CLOCK
7
DATAI
8
BCKI
9
WSI
10
L3MODE
11
NC
VDDD (C)
RESET
VDDA (PLL)
31 VSSA (PLL)
27 VDDA
26 VSSA
25 VSSA (DAC)
24 VREF
23
12
TC
BCKO
29
30
CLKOUT
28 NC
PREEM1
MUTE
44
RTCB
43
VDDD
42
PREEM0
41
NC
40
NC
37
WSO
36
DATAO
39
TEST2
38
NC
35
SELSTATIC
34
TEST1
13
SELCHAN
14
NC
15
SPDIF0
16
SPDIF1
17
VDDA (DAC)
18
VOUT L
19
SELCLK
20
SELSPDIF
21
LOCK
22
VOUT R
L3
INTERFACE
IEC 958
DECODER
DATA
OUTPUT
INTERFACE
CLOCK
AND
TIMING
CIRCUIT
DATA
INPUT
INTERFACE
AUDIO FEATURE PROCESSOR
INTERPOLATOR
NOISE SHAPER
DAC
DAC
63
HCD-CP500MD
7-20. IC PIN FUNCTION
• IC101 CXA2523AR RF AMPLLFLER (BD BOARD)
• IC101 CXA2523AR RF AMPLLFLER (BD BOARD)
Pin No.
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
Pin Name
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
Description
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2662R
Serial clock input from the CXD2662R
Latch signal input from the CXD2662R “L”: Latch
Stand by signal input “L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2662R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2662R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2662R
FM signal output of ADIP
ADIP signal comparator input ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2662R
I3 signal/temperature signal output to the CXD2662R
(Switching with a serial command)
Focus error signal output to the CXD2662R
Light amount signal output to the CXD2662R
RF/ABCD bottom hold signal output to the CXD2662R
RF/ABCD peak hold signal output to the CXD2662R
RF equalizer output to the CXD2662R
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
64
HCD-CP500MD
• IC151 CXD2662R DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR (BD BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
Pin Name
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
Description
Function FOK signal output to the system control (monitor output)
“H” is output when focus is on (Not used)
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output) (Not used)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control “L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system control
Laser power switching input from the system control “H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input) (Fixed at “L”)
Digital audio output (Optical output) (Open)
Serial data input (Fixed at “L”)
LR clock input “H” : Lch, “L” : R ch (Fixed at “L”)
Serial data clock input (Fixed at “L”)
Data input from the A/D converter
Data output to the D/A converter (Not used)
LR clock output for the A/D and D/A converter (44.1 kHz) (Not used)
Bit clock output to the A/D and D/A converter (2.8224 MHz) (Not used)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
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