Sony CMT-CP2W / HCD-CP2 (serv.man2) Service Manual ▷ View online
41
IC703
CXD2589Q
PWM
PWM
1
2 3
4 5 6
12
13
14
15 16 17
19 20
34
27
24
23
25
21
61
63
64
66
67
68
69
70
71
72
73
74
75
77
78
79
80
OSC
62
65
76
7 8 9
10
11
18
22
28
26
33
32
31
30
29
36
35
40
39
38
37
45
44
43
42
41
50
49
48
47
46
55
54 53 52 51
59 58 57
56
60
EFM
DEMODULATOR
ERROR
CORRECTOR
16k
RAM
D/A
INTERFACE
CLOCK
GENERATOR
SERVO
AUTO
SEQUENCER
CPU
INTERFACE
DIGITAL
OUT
SUB CODE
PROCESSOR
3rd-ORDER
NOISE SHAPER
OVER SAMPLING
DIGITAL FILTER
SERIAL-IN
INTERFACE
DIGITAL
CLV
OSC
DIGITAL
PLL
ASYMMETRY
CORRECTOR
LRCKI
LRCK
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
V16M
VCTL
VCTL
VCKI
VPCO1
TES1
TES0
PWMI
MDP
VDD
SYSM
AVSS
AVDD
XTAI
XVDD
AVSS
LOUT1
AIN1
AOUT1
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
XRST
XRST
VDD
VSS
EXCK
SBSO
SCOR
WFCK
ENPHI
EMPH
DOUT
C4M
XTSL
C2PO
GFS
XPCK
XUGF
VDD
VSS
BCKI
BCK
PCMDI
PCMD
VSS
LMUTE
RMUTE
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
XLON
FOK
VDD
VSS
42
– AUDIO Board –
IC602
µPC1330HA
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
– MAIN Board –
IC301
TDA7439
VREF
VOLUME
TREBLE
MIDDLE
BASS
SPEAKER
ATTENUATOR
MULTIPLEXER
GAIN AMP
IIC BUS
DECODER &
LATCH
SUPPLY
SDA
CREF
VS
AGND
ROUT
LOUT
SCL
DIG GND
TREBLE (R)
TREBLE (L)
MIN (L)
MOUT (L)
BOUT (L)
BIN (L)
BOUT (R)
BIN (R)
MOUT (R)
MIN (R)
INR
1
2 3 4
5
6
R-IN4
R-IN3
7
8
R-IN2
R-IN1
9
10
MULTIPLEXER
GAIN AMP
L-IN1
L-IN2
11 12
L-IN3
L-IN4
13 14
MUX OUT (L)
15
18
VOLUME
TREBLE
MIDDLE
BASS
SPEAKER
ATTENUATOR
INL
MUX OUT (R)
16
17
27
28
29
30
22 21 20 19
26 25 24 23
43
IC309, 402
KA3082
IC803 BU1924F-E2 (AEP, UK, North European models)
– AMP Board –
IC101, 201
TDA7296
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN
–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–
VS
STBY
MUTE
NC
NC
+PWVS
OUT
–
PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
44
7-21.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC802 CXP84332-168Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
A/B
O
Deck-A/B selection signal output to the HA12203NT (IC401) “L”: deck-A, “H”: deck-B
2
AMP-STBY
O
Standby on/off control signal output to the power amplifier (IC101, 201) “L”: standby mode
3
HI DUB REC
O
High speed dubbing control signal output to the HA12203NT (IC401)
4
C-XRST
O
Reset signal output to the CXA1992BR (IC701) and CXD2589Q (IC703) “L”: reset
5
SPEAK RELAY
O
Speaker protect relay drive signal output terminal “H”: relay on
6
AMP-MUTE
O
Muting on/off control signal output to the power amplifier (IC101, 201) “H”: muting on
7
REC-BIAS
O
Recording bias on/off selection signal output to the HA12203NT (IC401)
“L”: bias on, “H”: bias off
“L”: bias on, “H”: bias off
8
REC/PB
O
Recording/playback/pass selection signal output to the HA12203NT (IC401)
“L”: recording mode, “H”: pass, “Hi-z”: playback mode
“L”: recording mode, “H”: pass, “Hi-z”: playback mode
9
CAP MOTOR
CON
O
Capstan motor on/off control signal output terminal “H”: motor on
10
CAP MOTOR
H/L
O
High/normal speed selection signal output of the capstan motor
“L”: normal speed, “H”: high speed
“L”: normal speed, “H”: high speed
11
TRIG MOTOR
CON (A)
O
Deck-A side trigger motor drive signal output to the trigger motor drive (IC402)
“H”: motor on
“H”: motor on
12
TRIG MOTOR
CON (B)
O
Deck-B side trigger motor drive signal output to the trigger motor drive (IC402)
“H”: motor on
“H”: motor on
13
TRIG MOTOR
H/L
O
Trigger motor control signal output terminal
14
T-HALF (A)
I
Detection input from the deck-A cassette detect switch (S1003)
“L”: cassette in, “H”: no cassette
“L”: cassette in, “H”: no cassette
15
T-PLAY (A)
I
Detection input from the deck-A play detect switch (S1001) “H”: deck-A play
16
TC-SHUT (A)
I
Shut off detection signal input from the deck-A side reel pulse detector (Q1001)
17
TC-SHUT (B)
I
Shut off detection signal input from the deck-B side reel pulse detector (Q1002)
18
T-PLAY (B)
I
Detection input from the deck-B play detect switch (S1002) “H”: deck-B play
19
TU-TUNED
I
Tuning detection signal input from the tuner pack “L”: tuned
20
TU-DATA
O
PLL serial data output to the tuner pack
21
TU-CLK
O
PLL serial data transfer clock signal output to the tuner pack
22
TU-COUNT
I
PLL serial data input from the tuner pack
23
TU-CE
O
PLL chip enable signal output to the tuner pack
24
RDS-DATA
I
RDS serial data input from the RDS decoder (IC803)
(Used for the AEP, UK and North European models only)
(Used for the AEP, UK and North European models only)
25
RDS-ON
O
Power supply on/off control signal output of the tuner pack (+7.5V) and RDS decoder (IC803)
(Used for the AEP, UK and North European models only)
(Used for the AEP, UK and North European models only)
26
C/D
O
Command data output to the liquid crystal display driver (IC800)
27
LCD DATA
O
Serial data output to the liquid crystal display driver (IC800)
28
LCD CLK
O
Serial data transfer clock signal output to the liquid crystal display driver (IC800)
29
LCD CE
O
Chip enable signal output to the liquid crystal display driver (IC800)
30
RESET
I
System reset signal input from the reset signal generator (IC801) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL1
I
Main system clock input terminal (4.19 MHz)
32
XTAL1
O
Main system clock output terminal (4.19 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal (32.768 kHz)
35
TEX
I
Sub system clock input terminal (32.768 kHz)
36
AVSS
—
Ground terminal (for A/D converter)
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