Sony CMT-CP101 / CMT-CP101K / HCD-CP101 Service Manual ▷ View online
HCD-CP101
13
Note:
Confirm each contents of this section first of all. If the results are
not satisfied, do the adjustment.
not satisfied, do the adjustment.
1.
The adjustments should be performed with the rated power
supply voltage unless otherwise noted.
supply voltage unless otherwise noted.
2.
The adjustments should be performed in the order given in this
service manual. (As a general rule, playback circuit adjustment
should be completed before performing recording circuit
adjustment.)
service manual. (As a general rule, playback circuit adjustment
should be completed before performing recording circuit
adjustment.)
3.
The adjustments should be performed for both L-CH and R-
CH.
CH.
REC BIAS ADJUSTMENT
Procedure:
1. Mode: REC
1. Mode: REC
FUNCTION: VIDEO
2. Mode: Playback
3. Confirm playback the signal recorded in step 1 become speci-
fied values as follows.
If these values are out of specification values, adjust the RV101
(L-CH) and RV201 (R-CH) on the TC board to repeat steps
1and 2.
If these values are out of specification values, adjust the RV101
(L-CH) and RV201 (R-CH) on the TC board to repeat steps
1and 2.
Specified values: Playback output of 315 Hz to playback output
of 10 kHz:
± 0.5 dB
SECTION 5
ELECTRICAL ADJUSTMENTS
0 dB=0.775 V
DECK SECTION
attenuator
set
MAIN board
AUDIO IN MD (VIDEO) jack (SJ302)
L-CH, R-CH
AUDIO IN MD (VIDEO) jack (SJ302)
L-CH, R-CH
1) 315 Hz
2) 10 kHz
2) 10 kHz
50 mV (– 23.8 dB)
600
Ω
blank tape
CN-123
CN-123
AF OSC
+
–
–
set
recorded
portion
portion
MAIN board
SPEAKER terminals (SJ301)
L-CH, R-CH
SPEAKER terminals (SJ301)
L-CH, R-CH
level meter
Adjustment Location:
RV101 (L)
RV201 (R)
REC Bias
Adjustment
Adjustment
– TC BOARD (Component Side) –
HCD-CP101
14
IC103
TP (RF)
TP (VC)
– CD BOARD (Conductor Side) –
+
–
–
BD board
TP (RF)
TP (VC)
TP (VC)
oscilloscope
(DC range)
VOLT/DIV: 200 mV
TIME/DIV: 500 ns
TIME/DIV: 500 ns
level:
1.1
1.1
±
0.2 Vp-p
s
CD SECTION
Note:
1.
CD Block is basically constructed to operate without
adjustment.
adjustment.
2.
Use YEDS-18 disc (3-702-101-01) unless otherwise indicated.
3.
Use an oscilloscope with more than 10 M
Ω impedance.
4.
Clean the object lens by an applicator with neutral detergent
when the signal level is low than specified value with the
following checks.
when the signal level is low than specified value with the
following checks.
5.
Check the focus bias check when optical block is replaced.
FOCUS BIAS CHECK
Procedure :
1.
1.
Connect oscilloscope to TP (RF) and TP (VC) on the CD board.
2.
Press the
I/1
button to turn the power on, and press the
Z
(CD) button to open the CD disc tray.
3.
Put disc (YEDS-18) in and press the
u
(CD) button to play-
back.
4.
Confirm that oscilloscope waveform is as shown in the figure
below. (eye pattern)
A good eye pattern means that the diamond shape (
below. (eye pattern)
A good eye pattern means that the diamond shape (
) in the
center of the waveform can be clearly distinguished.
Checking Location:
HCD-CP101
15
15
I-V AMP
DETECTOR
(TRACKING)
(FOCUS)
2-AXIS DEVICE
LASER DIODE
A
B
C
D
F
E
6
7
8
10
11
4
2
1
5
10
6
7
D+5V
LD
PD
VCC
LD
PD
AUTOMATIC
POWER
CONTROL
Q101
5
RF
SUMMING
AMP
RF EQ
AMP
FOCUS
ERROR AMP
TRACKING
ERROR AMP
FI-V AMP
EI-V AMP
APC LD
AMP
APC PD
AMP
4
PD
16
14
13
22
21
RFO
FE
TE
LD ON
HOLD SW
LD
3
ASYMMETRY
CORRECTION
CORRECTION
EFM
DEMODULATOR
DIGITAL
PLL
51
49
48
RFAC
ASYI
ASYO
54 56 53 55
FILO
PCO
CLTV
FILI
ERROR
CORRECTOR
16k
RAM
INTERNAL BUS
D/A
INTERFACE
SERIAL
IN
INTERFACE
DIGITAL
FILTER
NOISE SHAPER
PWM
&
INTEGRATOR
DIGITAL
OUT
• SIGNAL PATH
: CD PLAY (ANALOG)
: CD PLAY (DIGITAL)
60
70
77
D OUT
AOUT1
AOUT2
AIN1
AIN2
51
51
71
76
72
75
LOUT1
LOUT2
BUFFER
CD-L
R-CH
SUBCODE
PROCESSOR
SERVO AUTO
SEQUENCER
CPU INTERFACE
2
5
7
6
20
8
1
14
SQCK
DATA
CLOK
XLAT
SCOR
SENS
SQSO
XLON
TO
MIRR/DFCT/FOK DETECTOR
IC101 (2/2)
9
27
SCLK
SSTP
26
MDP
S101
(LIMIT)
TE
FE
RFDC
SE
41 39 43
40
A/D
CONVERTER
FOCUS/TRACKING/SLED
PWM GENERATOR
FOCUS/TRACKING/SLED
SERVO DSP
MIRR/DFCT/FOK
DETECTOR
23 22
24
DFCT
MIRR
FOK
TO
SERVO
INTERFACE
IC101 (1/2)
IC101 (1/2)
DIGITAL SERVO
PROCESSOR
IC101 (2/2)
14
13
12
11
17
18
15
16
CH1OUTF
CH1OUTR
CH2OUTF
CH2OUTR
CH3OUTF
CH3OUTR
CH4OUTF
CH4OUTR
CH1FIN
CH1RIN
CH2 FIN
CH2RIN
CH3FIN
CH3RIN
2
3
5
6
24
23
MOTOR
DRIVE
MOTOR
DRIVE
COIL
DRIVE
MOTOR
DRIVE
COIL
DRIVE
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC102
M
M
M102
(SLED)
M101
(SPINDLE)
CH4SIN
25
33
32
31
30
28
29
FRDR
FFDR
SFDR
SRDR
TRDR
TFDR
MUTE
20
MUTE
Q802
Q804
Q806
Q808
Q807
Q805
SERVO
INTERFACE
DIGITAL
CLV
3
XRST
Q803
CD +8V
67
66
XTAL
XTAO
X101
16.9344MHz
TIMING
LOGIC
CLOCK
GENERATOR
OPTICAL
TRANSCEIVER
IC321
OPTICAL
DIGITAL OUT (CD)
DATA
DATA, CLK, LATCH,
SENS, SQSO
CLK
LATCH
SENS
SQSO
SQCK
XRST
HOLD
C SCOR
A
(Page 17)
H
(Page 16)
SQCK, XRST,
HOLD, C SCOR
J
(Page 16)
CD-ON
E
(Page 17)
RF AMP
FOCUS/TRACKING ERROR AMP
IC103
FILTER
DIGITAL SIGNAL PROCESSOR,
DIGITAL FILTER, D/A CONVERTER
IC101 (1/2)
OPTICAL
PICK-UP BLOCK
(KSM-213DCP)
M
M
Q802 – 808
CD ON SWITCH
• R-ch is omitted due to same as L-ch.
SECTION 6
DIAGRAMS
6-1.
BLOCK DIAGRAM – CD Section –
HCD-CP101
16
16
(AEP, UK)
TU1
TUNER PACK
(EXCEPT AEP, UK)
FM75Ω
ANENNA
AM
FM
75Ω
3
4
5
9
Q810
8
Q811
10
Q814
7
1
Q813
Q810, 811, 813, 814
TUNER ON SWITCH
4
13
14
2
DET AMP
Q812
16
12
2
X803
4.332MHz
RDS DECODER
IC804
D806
D401
(AEP, UK)
17
5
8
19
18
95
4
CAPSTAN/REEL
MOTOR DRIVE
Q601, 602
10
1
6
32
14
15
TRIGGER
PLUNGER DRIVE
Q603, 604
M
M
(TAPE DECK BLOCK)
6
5
10
2
33
M901
(LOADING)
(CAPSTAN/REEL)
OPEN
CLOSE
M
M
LOADING
MOTOR DRIVE
IC320
• SIGNAL PATH
: TUNER
: TAPE (PLAY)
: TAPE (REC)
FM ANT
ANT GND
AM ANT
ANT GND
L-CH
R-CH
R-CH
TUNED
DI
CK
CE
DO
FM DET
MUX
X1
X0
RDATA
RCLK
INPUT2
INPUT1
OUT2
OUT1
SYSTEM CONTROLLER
IC801 (1/2)
SQSO/RDS DATA
RDS-IN
TUNED
CD DATA/TU-DATA
CD-CLOCK/TU CLK
CD-LATCH/TU CE
CD-SENSE/TU COUNT
REC/PB
MOT-CON
SOL-CON
SENSOR
T-MODE
TC-SW
TRAY-OPEN
TRAY-CLOSE
TRAY-SW
S1
DISC TRAY
OPEN/CLOSE DETECT
• R-ch is omitted due to same as L-ch.
87
REC-MUTE
96
L-MUTE
34
BIN (L)
15
13
14
28
27
EQ-OUT (L)
26
PB-OUT
(L)
TAI (L)
MUTE
REC/PB AMP
IC401
A/B
MUTE
REC MUTE
24
23
REC-OUT
(L)
(L)
REC-IN
(L)
ALC
(L)
16
R-CH
R-CH
11
ALC
EQ
ALC
BIAS OSC
T401
REC BIAS
SWITCH
Q402, 403
COM +8V
BIAS OSC
Q401
REC BIAS
(L)
MUTING
Q100, 101
MUTING CONTROL
Q404, 405
RV101
REC BIAS
(R)
RV201
L-CH
R-CH
ERASE
R-CH
HRPE901
(REC/PB/ERASE)
R-CH
R-CH
T101
BIAS
TRAP
SQSO
SENS
LATCH
CLK
DATA
F
TU-ON
(Page 17)
H
DATA, CLK, LATCH,
SENS, SQSO
SENS, SQSO
(Page 15)
J
SQCK, XRST,
HOLD, C SCOR
HOLD, C SCOR
REC/PB
(Page 15)
G
(Page 17)
B
TU-L
(Page 17)
C
TC-L
(Page 17)
D
REC-L
(Page 17)
11
86
13
SQCK
XRST
HOLD
C SCOR
CD-CLK
C-XRST
HOLD
SCOR
100
6-2.
BLOCK DIAGRAM – TUNER/TAPE DECK Section –
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