Sony CMT-C5 / HCD-C5 Service Manual ▷ View online
69
HCD-C5
• IC151 CXD2662R
•
(DIGITAL SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER) (BD (MD) BOARD)
ATRAC ENCODER/DECODER) (BD (MD) BOARD)
I/O
Pin Name
Pin No.
Description
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
O
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DATI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
Focus OK signal output terminal “H” is output when focus is on (“L”: NG) Not used (open)
Track jump detection signal output to the MD mechanism controller (IC1001)
Busy monitor signal output to the MD mechanism controller (IC1001)
Spindle servo lock status monitor signal output to the MD mechanism controller (IC1001) (open)
Writing serial data signal input from the MD mechanism controller (IC1001)
Serial data transfer clock signal input from the MD mechanism controller (IC1001)
Serial data latch pulse signal input from the MD mechanism controller (IC1001)
Reading serial data signal output to the MD mechanism controller (IC1001)
Internal status (SENSE) output to the MD mechanism controller (IC1001)
Reset signal input from the MD mechanism controller (IC1001) “L”: reset
Subcode Q sync (SCOR) output to the MD mechanism controller (IC1001)
“L” is output every 13.3 msec Almost all, “H” is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller
(IC1001) “L” is output every 13.3 msec Almost all, “H” is output
Laser power selection signal input from the MD mechanism controller (IC1001)
“L”: playback mode, “H”: recording mode
Interrupt status output to the MD mechanism controller (IC1001)
Magnetic head on/off signal output to the over write head drive (IC181)
System clock signal (90.3168 MHz) input terminal
System clock signal (512Fs=90.3168 MHz) output terminal Not used (open)
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 90.3168 MHz (fixed at “H” in this set)
Digital audio signal input terminal when recording mode Not used
Digital audio signal input terminal when recording mode
Digital audio signal output terminal when playback mode
Recording data input from the A/D converter (IC1005)
L/R sampling clock signal (44.1 kHz) input from the D/A converter (IC1006), A/D converter
(IC1005)
Bit clock signal (2.8224 MHz) input from the D/A converter (IC1006), A/D converter (IC1005)
Recording data input terminal Not used (fixed at “L”)
Playback data output terminal Not used (open)
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
Bit clock signal (2.8224 MHz) output terminal Not used (open)
Clock signal (11.2896 MHz) output terminal Not used (open)
Power supply terminal (+3.3V) (digital system)
Address signal output to the D-RAM (IC152)
Address signal output to the D-RAM (IC152) (open)
Address signal output to the D-RAM (IC152)
Address signal output to the external D-RAM Not used (open)
Ground terminal (digital system)
Output enable signal output to the D-RAM (IC152) “L” active
Column address strobe signal output to the D-RAM (IC152) “L” active
Address signal output to the D-RAM (IC152)
Row address strobe signal output to the D-RAM (IC152) “L” active
Write enable signal output to the D-RAM (IC152) “L” active
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
70
HCD-C5
I/O
Pin Name
Pin No.
Description
I/O
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I
I (S)
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
D1
D0
D2
D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
TEST4
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Two-way data bus with the D-RAM (IC152)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
Playback EFM full-swing output terminal
Playback EFM asymmetry comparator voltage input terminal
Power supply terminal (+3.3V) (analog system)
Playback EFM asymmetry circuit constant current input terminal
Playback EFM RF signal input from the CXA2523AR (IC101)
Ground terminal (analog system)
Phase comparison output for master clock of the recording/playback EFM master PLL
Filter input for master clock of the recording/playback master PLL
Filter output for master clock of the recording/playback master PLL
Internal VCO control voltage input of the recording/playback master PLL
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
Focus error signal input from the CXA2523AR (IC101)
Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC101)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
Monitor output of the A/D converter input signal Not used (open)
Power supply terminal (+3.3V) (analog system)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
Ground terminal (analog system)
Sled error signal input from the CXA2523AR (IC101)
Tracking error signal input from the CXA2523AR (IC101)
Connected to the +3.3V power supply
nput terminal for the test Not used (fixed at “H”)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
Filter f0 control signal output to the CXA2523AR (IC101)
Serial data latch pulse signal output to the CXA2523AR (IC101)
Serial data transfer clock signal output to the CXA2523AR (IC101)
Writing serial data output to the CXA2523AR (IC101)
Control signal output to the reference voltage generator circuit for the laser automatic power
control
Input terminal for the test Not used (open)
Tracking servo drive PWM signal (–) output to the BH6511FS (IC141)
Tracking servo drive PWM signal (+) output to the BH6511FS (IC141)
Power supply terminal (+3.3V) (digital system)
Focus servo drive PWM signal (+) output to the BH6511FS (IC141)
Focus servo drive PWM signal (–) output to the BH6511FS (IC141)
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
Sled servo drive PWM signal (–) output to the BH6511FS (IC141)
Sled servo drive PWM signal (+) output to the BH6511FS (IC141)
Spindle servo drive PWM signal (–) output to the BH6511FS (IC141)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
71
HCD-C5
I/O
Pin Name
Pin No.
Description
O
I (S)
I
I
I
—
O
SPFD
FGIN
TEST1
TEST2
TEST3
DVSS
EFMO
94
95
96
97
98
99
100
Spindle servo drive PWM signal (+) output to the BH6511FS (IC141)
Input terminal for the test (fixed at “L”)
Ground terminal (digital system)
EFM signal output terminal when recording mode
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
72
HCD-C5
I/O
Pin Name
Pin No.
Description
—
—
—
—
—
—
—
I
I
I
O
I
O
—
I
—
I
I
I
I
—
—
O
—
I
—
—
—
I/O
I/O
O
I
O
—
—
—
—
—
—
—
—
I
O
I
O
I
I
(FLDT)
(FLCK)
(LEVEL-L)
(LEVEL-R)
—
BYTE
CNVSS
XIN-T
XOUT-T
S-RST
XOUT
VSS
XIN
VCC
NMI
DQSY
P-DOWN
SQSY
(KB-CLK)
(KB-DATA)
I2C-BUSY
(A1-OUT)
XINT
(BEEP)
(XELT)
(I2C-POWER)
I2C-CLK
I2C-DAT
SWDT
SRDT
SCLK
(KB-CLK-CTL)
(CLIP-TX0)
(CLIP-RX0)
(CLIP-CLK0)
(MUTE)
(ADA-RESET)
(ADA-LATCH)
EPM
(CLIP-SEL)
—
PROTECT
EEP-CLK
CE
EEP-WP
XBUSY(MNT2)
OUT-SW
1
2
3
4
5 to 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Not used
Not used
Not used
Not used
Not used
Data bus changed signal input (Connected to ground)
Processor mode selection terminal
Not used
Not used
System reset input
Main clock output (10MHz)
Ground
Main clock input (10MHz)
Power supply
Fixed at H (Pull-up)
Digital in sync signal input (Record system)
Power down detection signal input (L:Power down)
ADIP (MO) sync signal or subcode Q (PIT) sync signal input from the CXD2662R
(Playback system)
Not used
Not used
I2C cable connect check signal output
Not used
Interrupt status signal input from the CXD2662R
Not used
Not used
Not used
I2C serial clock input/output
I2C serial data input/output
Writing data signal output to the serial bus
Reading data signal input from the serial bus
Clock signal output to the serial bus
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used (Pull-down)
Not used
Not used
Recording protection tab detection signal input from the protection detection switch (H:Protect)
Clock signal output to the EEP-ROM
Fixed at H (Pull-up)
Write protect signal output to the EEP ROM (L:Write enable)
Busy signal input from the CXD2662R
Detection signal input from the loading out detection switch
• IC701 M30803MG-A03FP MASTER CONTROLLER (MD DIGITAL BOARD)
Click on the first or last page to see other CMT-C5 / HCD-C5 service manuals if exist.