Sony CFD-V77S (serv.man2) Service Manual ▷ View online
— 21 —
— 22 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
I/O
O
I
I
I
I
I
I
O
I
—
I/O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
O
—
I
I
I
I
I
I
I
I
I
O
—
Description
SubQ 80 bit and PCM peak, level data output. CD TEXT data output
Clock input for SQSO read out
System reset Resets at "L"
Mute input Mutes at "H"
Serial data input from CPU
Latch input from CPU Latches the serial data by trailing
Serial data transfer clock input from the CPU
SENS output. Outputs to the CPU
Clock input for SENS serial data reading
Digital power supply
Input/output for anti-shock (Not used)
Micro processing extension interface (input A)
Micro processing extension interface (input B)
Micro processing extension interface (output) "H" when resetting
WFCK output (Not used)
XUGF output. MNT1, RFCK output by switching of command (Not used)
XPCK output. MNT0 output by switching of command (Not used)
GFS output. MNT3, XROF output by switching of command (Not used)
C2PO output. GTOP output by switching of command (Not used)
"H" output when the sub-code sync S0 or S1 is detected
Truck number counting signal input/output
Mirror signal input/output
Defect signal input/output
Focus OK signal input/output
Samples the GFS at 460 Hz. "H" output when the GFS is "H". "L" output when the GFS is "L"
continuously three times
Or, input when LKIN = "1". Servo control output of spindle motor
Disc innermost circumference detection signal input
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital GND
Terminal for TEST Normally GND
Terminal for TEST Normally GND
X'tal selection input terminal "L" when X'tal is 16.9344 MHz. "H" when X`tal is 33.8688 MHz
Center point voltage input
Focus error signal input
Sled error signal input
Tracking error input
Center point servo analog input
RF signal input
Terminal for TEST Do not connect anything (Not used)
Analog ground
Pin Name
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLK
SENS
SCLK
V
DD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
V
SS
TEST
TES1
XTSL
VC
FE
SE
TE
CE
RFDC
ADIO
AV
SS
2-6. IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC702 CXD2587Q CD DIGITAL SIGNAL PROCESSOR
Pin No.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I
—
O
I
I
I
—
I
O
I
O
—
—
—
O
O
O
O
O
—
I
O
—
—
O
I
O
—
—
O
I
O
—
O
O
Description
Constant-current input for OP amplifier
Analog power supply
EFM full swing output ("L" = Vss, "H" = VDD)
Asymmetry comparator voltage input
Asymmetry circuit constant-current input
EFM signal input
Analog ground
VCO1 control voltage input for frequency-multiplication
Filter output for master PLL (Sleeve = digital PLL)
Filter input for master PLL
Charge pump for master PLL
Analog power supply
Digital ground
Digital power supply
Digital Out output terminal (Not used)
D/A interface LR clock output f = Fs (Not used)
D/A interface Serial data output (2`s COMP, MSB fast) (Not used)
D/A interface Bit clock output (Not used)
"H" output when the playback disc is emphasis ON. "L" output when emphasis OFF (Not used)
Power supply for master clock
Crystal oscillation circuit input terminal. When the master clock is input from the outside,
input from this terminal
Crystal oscillation circuit output terminal
Ground terminal for master clock
Analog power supply
L-ch: analog output terminal
L-ch: OPAMP input terminal
L-ch/LINE output terminal
Analog ground
Analog ground
R-ch: LINE output terminal
R-ch: OPAMP input terminal
R-ch: analog output terminal
Analog power supply
R-ch/"O" detection flag (Not used)
L-ch/"O" detection flag (Not used)
Pin Name
IGEN
AV
DD
ASYO
ASYI
BIAS
RFAC
AV
SS
CLTV
FILO
FILI
PCO
AV
DD
V
SS
V
DD
DOUT
LRCK
PCMD
BCK
EMPH
XV
DD
XTAI
XTAO
XV
SS
AV
DD
1
AOUT1
AIN1
LOUT1
AV
SS
1
AV
SS
2
LOUT2
AIN2
AOUT2
AV
DD
2
RMUT
LMUT
Note) • The PCMD is 2`s complement output of the MSB first.
• The GTOP is to monitor the protection status of the frame sync. ("H": sync protection window open)
• The XUGF is the frame sync obtained by the EFM signal and negative pulse. Signal before sync protection
• The XPCK is the inverted signal of the EFM PLL clock. The PLL is made so that the trailing edge and the changing point of the EFM signal agree.
• The GFS becomes "H" when the frame sync and inner protection timing agrre.
• The RFCK is the signal of 136 !!s cycle from the X`tal accuracy.
• The C2PO is the signal to indicate the error status of the data.
• The XROF is the signal when the 16K RAM exceeds the jitter margin of +/- 4frames.
COMMANDBIT
OUTPUT DATA
MTSL1
0
0
1
MTSL0
0
1
0
XPCK
MNT0
XPCK
XUGF
MNT1
RFCK
GFS
MNT3
XROF
C2PO
C2PO
GTOP
Combination of MONITOR output
— 21 —
— 22 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
I/O
O
I
I
I
I
I
I
O
I
—
I/O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
O
—
I
I
I
I
I
I
I
I
I
O
—
Description
SubQ 80 bit and PCM peak, level data output. CD TEXT data output
Clock input for SQSO read out
System reset Resets at "L"
Mute input Mutes at "H"
Serial data input from CPU
Latch input from CPU Latches the serial data by trailing
Serial data transfer clock input from the CPU
SENS output. Outputs to the CPU
Clock input for SENS serial data reading
Digital power supply
Input/output for anti-shock (Not used)
Micro processing extension interface (input A)
Micro processing extension interface (input B)
Micro processing extension interface (output) "H" when resetting
WFCK output (Not used)
XUGF output. MNT1, RFCK output by switching of command (Not used)
XPCK output. MNT0 output by switching of command (Not used)
GFS output. MNT3, XROF output by switching of command (Not used)
C2PO output. GTOP output by switching of command (Not used)
"H" output when the sub-code sync S0 or S1 is detected
Truck number counting signal input/output
Mirror signal input/output
Defect signal input/output
Focus OK signal input/output
Samples the GFS at 460 Hz. "H" output when the GFS is "H". "L" output when the GFS is "L"
continuously three times
Or, input when LKIN = "1". Servo control output of spindle motor
Disc innermost circumference detection signal input
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital GND
Terminal for TEST Normally GND
Terminal for TEST Normally GND
X'tal selection input terminal "L" when X'tal is 16.9344 MHz. "H" when X`tal is 33.8688 MHz
Center point voltage input
Focus error signal input
Sled error signal input
Tracking error input
Center point servo analog input
RF signal input
Terminal for TEST Do not connect anything (Not used)
Analog ground
Pin Name
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLK
SENS
SCLK
V
DD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
V
SS
TEST
TES1
XTSL
VC
FE
SE
TE
CE
RFDC
ADIO
AV
SS
2-6. IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC702 CXD2587Q CD DIGITAL SIGNAL PROCESSOR
Pin No.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I
—
O
I
I
I
—
I
O
I
O
—
—
—
O
O
O
O
O
—
I
O
—
—
O
I
O
—
—
O
I
O
—
O
O
Description
Constant-current input for OP amplifier
Analog power supply
EFM full swing output ("L" = Vss, "H" = VDD)
Asymmetry comparator voltage input
Asymmetry circuit constant-current input
EFM signal input
Analog ground
VCO1 control voltage input for frequency-multiplication
Filter output for master PLL (Sleeve = digital PLL)
Filter input for master PLL
Charge pump for master PLL
Analog power supply
Digital ground
Digital power supply
Digital Out output terminal (Not used)
D/A interface LR clock output f = Fs (Not used)
D/A interface Serial data output (2`s COMP, MSB fast) (Not used)
D/A interface Bit clock output (Not used)
"H" output when the playback disc is emphasis ON. "L" output when emphasis OFF (Not used)
Power supply for master clock
Crystal oscillation circuit input terminal. When the master clock is input from the outside,
input from this terminal
Crystal oscillation circuit output terminal
Ground terminal for master clock
Analog power supply
L-ch: analog output terminal
L-ch: OPAMP input terminal
L-ch/LINE output terminal
Analog ground
Analog ground
R-ch: LINE output terminal
R-ch: OPAMP input terminal
R-ch: analog output terminal
Analog power supply
R-ch/"O" detection flag (Not used)
L-ch/"O" detection flag (Not used)
Pin Name
IGEN
AV
DD
ASYO
ASYI
BIAS
RFAC
AV
SS
CLTV
FILO
FILI
PCO
AV
DD
V
SS
V
DD
DOUT
LRCK
PCMD
BCK
EMPH
XV
DD
XTAI
XTAO
XV
SS
AV
DD
1
AOUT1
AIN1
LOUT1
AV
SS
1
AV
SS
2
LOUT2
AIN2
AOUT2
AV
DD
2
RMUT
LMUT
Note) • The PCMD is 2`s complement output of the MSB first.
• The GTOP is to monitor the protection status of the frame sync. ("H": sync protection window open)
• The XUGF is the frame sync obtained by the EFM signal and negative pulse. Signal before sync protection
• The XPCK is the inverted signal of the EFM PLL clock. The PLL is made so that the trailing edge and the changing point of the EFM signal agree.
• The GFS becomes "H" when the frame sync and inner protection timing agrre.
• The RFCK is the signal of 136 !!s cycle from the X`tal accuracy.
• The C2PO is the signal to indicate the error status of the data.
• The XROF is the signal when the 16K RAM exceeds the jitter margin of +/- 4frames.
COMMANDBIT
OUTPUT DATA
MTSL1
0
0
1
MTSL0
0
1
0
XPCK
MNT0
XPCK
XUGF
MNT1
RFCK
GFS
MNT3
XROF
C2PO
C2PO
GTOP
Combination of MONITOR output
— 23 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15–21
22
23
24
25
26
27
28
29
30
31
32
33
34
35–37
38–41
42–55
56–71
72
73, 74
75–77
78–80
I/O
I
I
O
—
I
O
O
I
O
O
O
O
O
I
—
I
I
—
—
—
—
—
—
I
I
O
—
O
—
O
O
—
—
—
—
—
Description
Sub-code sync detection signal
CD lid detection H: OPEN L: CLOSE
Audio signal MUTE H: MUTE ON L: MUTE OFF
Not used (OPEN)
SENS signal
SENS serial data reading clock
Clock for SQSO reading
SUB-Q serial data
System reset
Serial data transfer clock
Latches the serial data by trailing
Serial data
ON/OFF control of LPC
TAPE recording detection L:REC
Not used (OPEN)
AD processing (PLAY/PAUSE, STOP, AMS+, AMS-)
AD processing (MODE, DISP/ENT)
Not used (OPEN)
Not used
Not used
Not used
Not used (OPEN)
Not used (OPEN)
Micro processing reset L: reset
4. 19 MHz
4. 19 MHz
Ground
Bias control for LCD
Bias power supply for LCD
Common signal output for LCD
Segment signal output for LCD
Not used (OPEN)
Positive power supply +5V
Not used (Connected to ground.)
Not used (OPEN)
Not used (Connected to ground.)
Pin Name
SCOR
DOOR
MUTE
NC
SENS
SCLK
SQCK
SQSO
XRST
CLOCK
LATCH
DATA
AGCCONT
REC
NC
KEY-1
KEY-2
NC
FOK/DF2
FZC/DFS
SRC/DF1
NC
NC
RST
EXTAL
XTAL
V
SS
VL
VLC3–1
COM0–3
SEG0–13
NC
VDD
NC
NC
NC
• MAIN BOARD IC801 CXP83516-605Q LCD DRIVE/SYSTEM CONTROL
— 24 —
2-7. IC BLOCK DIAGRAMS
IC1 CXA1238S
30
29
4
5
6
7
8
9
10
11
12
13 14 15
3
2
1
28 27
26 25 24 23 22 21
20
19
18
17
16
REG
FM FRONT-END
AM FRONT-END
VCO
MPX REG.
1/2
COUNTER
1/2
COUNTER
PD1
PD2
MUTING
DECODER AMP
MONO/ST
SELECT
RIPPLE
FILTER
AUTOBLEND
BAND PASS
MUTE
TUNING
INDICATOR
FM IF/
DISCRI
AM
IF/DET
GND
PLL LPF2
MPX REG
VCO
FM
DISCRI
MUTE
AM OSC
AFC
FM OSC
REG
FM RF
AM RF IN
FM RF IN
BAND SELECT
AM IF IN
FM IF IN
TUNE IND
GND
VCC
L CH OUT
R CH OUT
ST IND/
VCO CHECK
PILOT DET LPF2
PILOT DET LPF2
PLL LPF1
AGC AFC2
AGC AFC1
RIPPLE
FIL
TER
FM GND
FM/AM
FE OUT
21
22
23
24
2
3
5
4
6
7
8
9
10
1
11
12
13
14
15
16
17
18
19
20
LOGIC
7dB
26dB
26dB
7dB
ALC1
ALC2
DET
MIC
AMP1
1k
10k
NAB
AMP2
NAB
AMP1
ON
MUTE
MUTE
MUTE
BUF AMP
A2
BUF AMP
A1
BUF AMP
B1
BUF AMP
B2
TAPE
TAPE
–––––
TAPE
–––––
LINE
RADIO
10k
10k
10k
1k
1k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
15k
6k
1k
6k
LINE
RADOI
TAPE
REC
AMP1
REC
AMP2
REF AMP
2.1
ON
ON
MONITOR
AMP
MONITOR
AMP
LIN
MIC
I/EX
L. RAD
L. LO
REC
TAPE
R. LIN
MIC
IN
R. LO
LINE
R. RAD
VCC
MIC
NF
R. PO
R. NF
R. RO
R. IN
GND
REF
L. IN
L. RO
L. NF
L. PO
AGC
IC301 TA2068N
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