Sony CFD-S40CP Service Manual ▷ View online
16
CFD-S40CP
T1: MW/LW
IF Adjustment
IF Adjustment
L3: LW Tracking
Adjustment
(AEP, UK)
Adjustment
(AEP, UK)
L3: MW Tracking
Adjustment
(AEP, UK)
Adjustment
(AEP, UK)
CT5: LW Tracking
Adjustment
(AEP, UK)
Adjustment
(AEP, UK)
CT3: AM (MW) Tracking
Adjustment
Adjustment
L4: AM Tracking Adjustment (US, CND, Korean, Taiwan)
L4: LW Frequency Coverage Adjustment (AEP, UK)
L4: LW Frequency Coverage Adjustment (AEP, UK)
L2: FM Frequency
Coverage Adjustment
L1
CT1
FM Tracking Adjustment
TUNER BOARD
(Component side)
(Component side)
Adjustment Location :
CD BOARD
(SIDE A)
IC1007
RV1001:Focus Erorr Adjustment
IC1006
Ver 1.1 12001.07
17
CFD-S40CP
Pin No.
Pin name
I/O
Description
1
C-DOOR
I
Door open/close switch (S701) input
2
RMC
I
Remote control signal input
3
ES-EMG
O
Emergency signal output
4
B/C-MUTE
O
Radio mute signal output
5
REC-MUTE
O
Mute signal output on switching function
6
ES-CS
I
CD chip select signal input
7
ES-CLK
I
CD clock signal input
8
ES-ID
I
CD serial data signal input
9
ES-OD
O
CD serial data signal output
10
P-CON
O
Power control signal output
11
BATTCHK
O
Battery voltage check signal output
12
MP3LIGHT
O
MP3 light signal output
13
A-MUTE
O
Audio mute signal output
14
R-COUNT
O
Radio count signal output
15
R-CLOCK
O
Radio control clock signal output
16
R-DATA
O
Radio control data signal output
17
R-CE
O
Radio latch signal output
18
V-LATCH
O
Data latch signal output to LC75342 (VOL IC)
19
V-DATA
O
Data signal output to LC75342 (VOL IC)
20
V-CLOCK
O
Clock signal output to LC75342 (VOL IC)
21
AC/DC CHK
I
AC/DC check signal input
22 – 24
KEY-1 – 3
I
Key input terminal of A/D port
25
VM REG
I
Battery center voltage input terminal of A/D port
26
VH REG
I
Battery voltage input terminal of A/D port
27
BL CONT/INIT
O
Initial setting signal and LCD back light control signal output
28
M. B/MODE CHECK
I
Reading specification and MEGA BASS signal input terminal (A/D port)
29
SHIFT CLOCK
O
Clock frequency shift change signal output
30
RST
I
System reset signal input
31
EXTAL
I
Crystal oscillator terminal (4.0MHz)
32
XTAL
O
Crystal oscillator terminal (4.0MHz)
33
VSS
—
Ground terminal
34
VL
O
LCD bias control signal output
35
VLC3
—
LCD bias voltage terminal
36
VLC2
—
LCD bias voltage terminal
37
VLC1
—
LCD bias voltage terminal
38 – 41
COM0 – 3
O
LCD common signal output
42 – 69
SEG0 – 27
O
LCD segment signal output
70
RADIO
O
Radio function signal output
71
CD
O
CD function signal output
72
VDD
—
Power supply terminal
73
REC
I
Tape recording function signal input
74
NC
—
Not used (Connect to ground)
75
NC
—
Not used (Open)
76, 77
ISS-1, -2
O
ISS select signal output
78
TC-PLAY
I
Tape play switch (S321) input
79
JOG +
I
JOG dial key (+) signal input
80
JOG –
I
JOG dial key (–) signal input
SECTION 5
DIAGRAMS
5-1. EXPLANATION OF IC TERMINALS
IC801 CXP83620-029Q SYSTEM CONTROL
18
CFD-S40CP
Pin No.
Pin name
I/O
Description
1
VDD3
—
Power supply terminal
2
RAS#
O
Strobe signal for M11B41256A (DRAM) column address output (Active: L)
3
DWE#
O
Write enable signal output to M11B41256A (DRAM) (Active: L)
4 – 12
DA0 – 8
O
Address bus output to M11B41256A (DRAM)
13 – 28
DBUS0 – 15
I/O
Data bus terminal to/from M11B41256A (DRAM)
29
RESET#
I
System reset signal input
30
VSS
—
Ground terminal
31
VDD3
—
Power supply terminal
32 – 39
YUV0 – 7
O
Not used (Open)
40
VSYNC
I/O
Not used (Open)
41
HSYNC
I/O
Not used (Open)
42
CPUCLK
I
System clock signal input from ES3889 (DSP)
43
PCLK2X
I/O
Clock for pixel double signal (27MHz)
44
PCLK
I/O
Clock for pixel signal (13.5MHz)
45
AUX0
I
GFS signal input from CXD3068Q
46
AUX1
O
FOK signal output
47
AUX2
O
CD serial data signal output
48
AUX3
O
CPU interface clock signal output to CXD3068Q
49
AUX4
O
I data request signal output
50
VSS
—
Ground terminal
51
VDD3
—
Power supply terminal
52
AUX6
O
CD serial clock signal output
53
AUX5
O
System data strobe signal output
54
AUX7
O
CD serial chip select signal output
55 – 62
LD0 – 7
I/O
Data bus to/from RISK interface
63
LWR#
O
Not used (Open)
64
LOE#
O
Output enable signal output to RISK interface
65
LCS3
O
Chip enable signal output to HT27C020 (ROM)
66
LCS1
O
Clock signal output to system data
67
LCS0
O
Clock signal output to CXD3068Q (DSP)
68 – 79
LA0 – 11
I/O
Address bus to/from HT27C020 (ROM)
80
VSS
—
Ground terminal
81
VPP
—
Protection voltage terminal
82 – 87
LA12 – 17
I/O
Address bus to/from HT27C020 (ROM)
88
ACLK
I/O
Master clock signal of audio DAC data
89
AOUT/SEL-PLL0
I/O
Serial data to/from audio interface
90
ATCLK
O
Transferring audio bit clock signal output
91
ATFS/SEL-PLL1
O
Sync. signal output of transferring audio frame signal
92
DA9/DOE#
O
Output enable signal output to M11B41256A (DRAM)
93
AIN
I
Serial data input from audio interface
94
ARCLK
I
Bit clock signal input from audio receiver
95
ARFS
I
Frame sync. signal input from audio receiver
96
TDMCLK
I
Serial clock input from CXD3068Q
97
TDMDR
I
Serial data input from CXD3068Q
98
TDMFS
I
Frame sync. signal input from CXD3068Q
99
CAS#
O
Strobe signal for M11B41256A (DRAM) row address output (Active: L)
100
VSS
—
Ground terminal
IC1001 ES3880 MP3 DECOMPRESSION
CFD-S40CP
19
19
Pin No.
Pin name
I/O
Description
1
VSS
—
Ground terminal
2
NC
—
Not used (Connected to ground)
3
NC
—
Not used (Open)
4
NC
—
Not used (Connected to VCC)
5
VCC
—
Power supply terminal
6
DSC C
I
Clock signal input of inner register
7
AUX0
I
CD serial data signal input
8
DSC D0
I/O
System data bus (Bit0)
9
AUX1
O
CD bias switch signal output
10
DSC S
I
System data strobe signal input
11
AUX2
O
CD LD on signal output
12
DCLK/EXT CLK
O
System clock signal output
13
RESET B
I
Reset signal input for video
14
AUX7/VFD DI
I
SENC input from CXD3068Q
15
MUTE
O
Not used (Open)
16
VCC
—
Power supply terminal
17
MCLK
I
Master clock of audio
18
AUX8/VFD CLK
—
Not used (Open)
19
TWS/SPLL OUT
I
Transferring audio frame sync. signal input
20
AUX9/SQAD
I
SQSO signal input from CXD3068Q
21
TSD
I
Transferring audio data input
22
TBCK
I
Transferring audio bit clock signal input
23
RWS/SEL PLL1
O
Frame sync. signal output of audio receiver
24
RSTOUT B
O
System reset signal output
25, 26
VSS
—
Ground terminal
27, 28
NC
—
Not used (Open)
29, 30
GND
—
Ground terminal
31
VSS
—
Ground terminal
32
VCC
—
Power supply terminal
33
RSD/SEL PLL0
O
Serial data output of audio interface
34
AUX10/SQCK
O
SQCK signal output to CXD3068Q
35
AUX11/IRQ
I
I data request signal input
36
AUX12/C2PO
I
Clock for pixcel double signal input
37
RBCK/SER IN
O
Frame sync. signal output of audio receiver
38
AUX13/SP
O
Reset signal output to CXD3068Q
39
AUX14/SOSI
I
SCOR signal input from CXD3068Q
40
AUX15/IR
I
CD mute signal input
41
VSSAA
—
Ground terminal of analog port
42
VCM
I
Reference voltage output of ADC common mode
43
VREFP
I
Not used (Connected to ground)
44
VCCAA
—
Power supply terminal of analog port
45
AOR +
O
Audio signal output (R-CH)
46
AOR –
O
Audio signal output (R-CH)
47
AOL –
O
Audio signal output (L-CH)
48
AOL +
O
Audio signal output (L-CH)
49, 50
MIC1, 2
I
Not used (Open)
51
VSSAA
—
Ground terminal of analog port
52
VREF
I
Not used (Open)
53
VREFM
I
Power supply terminal
54
REST
I
Not used (Open)
55
COMP
I
Not used (Open)
56, 57
VSSAV
—
Ground terminal
58
CDAC
O
Not used (Open)
59, 60
VCCAV
—
Power supply terminal
61
YDAC
O
Not used (Open)
62, 63
VSSAV
—
Ground terminal
64
VDAC
O
Not used (Open)
IC1002 ES3889 DIGITAL SIGNAL PROOCESSOR, D/A CONVERTER
Pin No.
Pin name
I/O
Description
65
ACAP
I
Connected to capacitor
66
VCC
—
Power supply terminal
67
AUX6/VFD DO
O
Interrupt signal output to CXD3068Q
68
AUX5
O
System data output to CXD3068Q
69
AUX4
I
Not used (Open)
70
AUX3
O
AGC control signal output for CD RF amp.
71
XOUT
O
Crystal oscillator terminal
72
VSS
—
Ground terminal
73
VCC
—
Power supply terminal
74
XIN
I
Crystal oscillator terminal
75
VSS
—
Ground terminal
76
NC
—
Not used (Open)
77
VSS
—
Ground terminal
78
VCC
—
Power supply terminal
79
PCLK
I/O
Clock for pixel signal (13.5MHz)
80
2XPCLK
I/O
Clock for pixel double signal (27MHz)
81
DSC D7
I/O
System data bus (Bit7)
82
HSYN B
O
Not used (Open)
83
DSC D6
I/O
System data bus (Bit6)
84
VSYN B
O
Not used (Open)
85
DSC D5
I/O
System data bus (Bit5)
86 – 89
YUV7 – 4
I
Not used (Connected to ground)
90
VCC
—
Power supply terminal
91
VSS
—
Ground terminal
92
YUV3
I
Not used (Connected to ground)
93
DSC D4
I/O
System data bus (Bit4)
94
YUV2
I
Not used (Connected to ground)
95
DSC D3
I/O
System data bus (Bit3)
96
YUV1
I
Not used (Connected to ground)
97
DSC D2
I/O
System data bus (Bit2)
98
YUV0
I
Not used (Connected to ground)
99
DSC D1
I/O
System data bus (Bit1)
100
VSS
—
Ground terminal
PRIMARY board
SECONDARY board
HEADPHONE board
LCD board
CONTROL board
CD board
TUNER board
BATTERY COMMON board
CD MOTOR board
BATTERY board
MAIN board
TC board
LAMP board
• Circuit Boards Location
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