Sony CFD-S35CP (serv.man3) Service Manual ▷ View online
17
CFD-S35CP
• IC Block Diagrams
IC201 TK63115SCL-G@GT (BD90 Board)
IC401 BA5826SFP-E2 (BD90 Board)
VDD 1
GND 2
VOUT
3
V REF
ON/OFF
CONTROL
THERMAL &
OVER CURRENT
PROTECTION
CE
5
4 NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
24
23
22
21
20
19
18
17
16
15
25
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
GND
IN4
IN4'
BIAS
VCC
VCC
IN3'
IN3
VOL+
VOL-
RESET
OPIN
VO1-
REGB
VO1+
IN1
RESET
REGOUT
MUTE
GND
IN2'
IN2
VO2+
VOL-
GND
OPOUT
MUTE
VCC
VCC
13.3K
13.3K
13.3K
13.3K
100
10K
10K
10K
T.S.D.
REGULATOR,BIAS
DROP
VO3-
VO3+
CH3
CH4
CH2
CH1
18
CFD-S35CP
IC302 BD3870FS-E2 (MAIN Board (1/2))
IC803 S-24CS02AFJ-TB-G (MAIN Board (2/2))
VIN1
VIN2
SEL2
SEL1
A1
A2
B1
B2
C1
C2
FILTER
GND
CAP
TNF1
TNF2
BNF2
BOUT2
BNF1
BOUT1
OUT1
OUT2
SI
SC
VCC
BASS1
f
0
=80Hz
BASS2
f
0
=80Hz
21
20
19
18
17
16
15
14
13
TREBLE2
f
0
=8kHz
22
TREBLE1
f
0
=8kHz
23
SURROUND
24
1
2
3
4
LOGIC
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
5
6
7
8
9
10
11 12
START/STOP
DETECT CIRCUIT
HIGH VOLTAGE
GENERATOR
DATA OUTPUT/
ACK OUTPUT/
CONTROL CIRCUIAT
DATA
REGISTER
EEPROM
X DECODER
SELECTOR
DEVICE
ADDRESS
COMPARATOR
SERIAL CLOCK
CONTROL CIRCUIT
ADDRESS
COUNTER
COUNTER
Y DECODER
LOAD
COMP
LOAD
R/W
DOUT
DIN
A0
A1
A2
GND
INC
1
2
3
4
SDA
SCL
WP
VCC
5
6
7
8
19
CFD-S35CP
• IC Pin Descriptions
BD90 BOARD IC101 TC94A70FG-006 (RF AMP, DSP, MP3)
BD90 BOARD IC101 TC94A70FG-006 (RF AMP, DSP, MP3)
Pin No.
Pin Name
I/O
Pin Description
1
AVSS3
—
Ground
2
RFZi
I
RF ripple zero cross signal input
3
RFRP
O
RF ripple signal output
4
SBAD/RFDC
O
Not used (Open)
5
FEi
O
Not used (Open)
6
TEi
O
Tracking error signal output
7
TEZi
I
Tracking error signal input
8
AVDD3
—
Power supply (+3.3V)
9
FOo
O
Focus servo equalizer output
10
TRo
O
Tracking servo equalizer output
11
VREF
—
REF of analog power supply
12
FMO
O
Feed servo equalizer output
13
DMO
O
Disc servo equalizer output
14
VSSP3
—
Ground
15
VCOi
O
PD output
16
VDDP3
—
Power supply (+3.3V)
17
VDD1
—
Power supply (+1.5V)
18
VSS1
—
Ground
19
FGiN
I
FG signal input (Not used (Fixed to “L”))
20
IO0(/HSO)
I
Play speed mode flag input
21
IO1(/UHSO)
I
Not used (Open)
22
XVSS3
—
Ground
23
XI
I
System clock input (16.934MHz)
24
XO
O
System clock output (16.934MHz)
25
XVDD3
—
Power supply (+3.3V)
26
DVSS3
—
Ground
27
RO
O
Audio R-ch signal output
28
DVDD3
—
Power supply (+3.3V)
29
DVR
I
REF voltage input (Used DAC)
30
LO
O
Audio L-ch signal output
31
DVSS3
—
Ground
32
VDDT3
—
Power supply (+3.3V)
33
VSS1
—
Ground
34
VDD1
—
Power supply (+1.5V)
35
VDDM1
—
Power supply (SRAM +1.5V)
36
SRAMSTB
I
1M bit SRAM standby input (Not used (Pull down))
37
RST
I
Reset signal input
38
BUS0
I/O
CD-DSP-MP3 serial data input/output
39
BUS1
I/O
CD-DSP-MP3 serial data input/output
40
BUS2(SO)
I/O
CD-DSP-MP3 serial data input/output
41
BUS3(SI)
I/O
CD-DSP-MP3 serial data input/output
42
BUCK(CLK)
I
BUS clock input (Serial clock input)
43
CCE
I
Clip enable signal input (U-com interface)
44
TEST
I
Test setting (Not used (Fixed to “L”))
45
IRQ
I
Cut in DSP input (Not used (Pull down))
46
AoUT3(PO4)
O
Not used (Open)
Ver. 1.9
20
CFD-S35CP
47
AoUT2(PO5)
O
Not used (Open)
48
PiO0
O
MP3 REQ signal output
49
PiO1
I
Not used (Open)
50
PiO2
I
Not used (Open)
51
PiO3
I
Not used (Open)
52
VSS1
—
Ground
53
VDDT3
—
Power supply (+3.3V)
54
SBSY
O
Sub code block sync output
55
SBOK/FOK
O
Not used (Open)
56
IPF
O
Not used (Open)
57
SFSY/LOCK
O
Not used (Open)
58
ZDET
O
DAC zero data detect flag output (Not used (Open))
59
GPIN
I
General purpose input (Not used (Pull down)
60
MS
I
U-com I/F mode select input (Pull up)
61
DOUT(PO6)
O
Not used (Open)
62
AOUT1(PO7)
O
Not used (Open)
63
BCK(PO8)
O
Not used (Open)
64
LRCK(PO9)
O
Not used (Open)
65
AIN(PI4)
I
Data input (Used DAC) (Not used (Fixed to “L”))
66
BCKi(PI5)
I
Bit clock input (Used DAC) (Not used (Fixed to “L”))
67
LRCKi(PI6)
I
Channel clock input (Used DAC) (Not used (Fixed to “L”))
68
VDD1
—
Power supply (+1.5V)
69
VSS1
—
Ground
70
AWRC
O
Not used (Open)
71
PVDD3
—
Power supply (+3.3V)
72
PDo
O
Phase error signal of EFM signal and PLCK signal output
73
TMAXS
O
Not used (Open)
74
TMAX
O
TMAX detect signal output
75
LPFN
I
AMP (PLL-LPF) reverse input
76
LPFo
O
AMP (PLL-LPF) signal output
77
PVREF
O
1.65V REF power output
78
VCOF
O
VCO filter output
79
PVSS3
—
Ground (+3.3V)
80
SLCo
O
EFM slice level output
81
RFi
I
RF signal input
82
RFRPi
I
RF ripple signal input
83
RFEQo
O
RF equalizer output
84
VRo
O
1.65V REF voltage output
85
RESiN
I
REF resister input
86
VMDiR
—
REF voltage of APC circuit output
87
TESTR
O
LPF output (RFEQO offset correct)
88
AGCi
I
RF signal adjustment AMP input
89
RFo
O
RF signal AMP output
90
RVDD3
—
Power supply (+3.3V)
91
LDo
O
Laser diode AMP output
92
MDi
I
Monitor photo diode AMP input
93
RVSS3
—
Ground
Pin No.
Pin Name
I/O
Pin Description
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