Sony CFD-S20CP Service Manual ▷ View online
16
CFD-S20CP
Q701
R702
R704
R706
R707
R708
R709
R711
R729
R730
R745
C701
C7
C705
C706
C740
C710
C711
C712
C713
C714
C716
C717
C718
C719
C720
C721
R710
R755
R757
R759
R724
R725
R726
R727
R728
R732
R733
R734
R735
R736
R737
R740
R1001
R1002
R1003
R1004
R10
C708
C746
C742
C743
C744
C760
C761
C762
C763
C764
C766
C767
C737
C732
C733
C722
C756
C1066
C1067
C1068
C1069
C10
C1074
FB701
R763
R764
R723
IC701
R765
FB1001
FB1002
FB703
FB704
CNP701
C707
C715
C709
TP(RF)
TP
(VREF)
TP
(FE)
TP
(TE)
TX
TY
FX
FY
SPX
SPY
SLX
SLY
TP
(RF)
TP
(VREF)
TP
(TE)
– CD board (conductor side) –
Adjustment Location:
CD SECTION
CD section adjustments are done automatically in this set.
In case of operation check, confirm that focus bias.
In case of operation check, confirm that focus bias.
FOCUS BIAS CHECK
1. Connect the oscilloscope between IC701 pin 4 and pin qa (or
TP (RF) and TP (VREF)).
2. Insert the disc (YEDS-18). (Part No. : 3-702-101-01)
3. Press the N X (CD) button.
4. Confirm that the oscilloscope waveform is as shown in the
3. Press the N X (CD) button.
4. Confirm that the oscilloscope waveform is as shown in the
figure below. (eye pattern)
A good eye pattern means that the diamond shape ( ) in the
center of the waveform can be clearly distinguished.
A good eye pattern means that the diamond shape ( ) in the
center of the waveform can be clearly distinguished.
• RF signal reference waveform (eye pattern)
Test Point:
RF level :
0.85
0.85
±
0.2 Vp-p
VOLT/DIV : 50 mV (10 : 1 probe in use)
TIME/DIV : 500 nS
TIME/DIV : 500 nS
When observing the eye pattern, set the oscilloscope for AC range
and raise vertical sensitivity.
and raise vertical sensitivity.
L4
TP (FM IN)
(CONDUCTOR SIDE)
CT1
IC1
IC2
CT3
L1
L2
T2
T1
L3
– MAIN board (component side) –
L4
AM
FREQUENCY
COVERAGE
ADJUSTMENT
L2
FM
FREQUENCY
COVERAGE
ADJUSTMENT
CT3, L3
AM
TRACKING
ADJUSTMENT
CT1, L1
FM
TRACKING
ADJUSTMENT
T1
AM
IF
ADJUSTMENT
T2
FM
IF
ADJUSTMENT
TP (VT)
(CONDUCTOR SIDE)
17
CFD-S20CP
1
LRSY
I
CD L/R clock input
2
ADDATA
O
Audio data output
3
ADBCK
O
Audio bit clock output
4
ADLRCK
O
Audio L/R clock output
5
C2FIN
I
CD C2 error flag input
6
VSS
—
Ground
7
CKIN
I
System clock (16.9344 MHz) input
8
VSS
—
Ground
9
CKOUT
O
Clock (384Fs) output for external DF/DAC.
10
VSS
—
Ground
11
DVDD1
—
Digital power supply pin for I/O.
12
PW
I
CD subcode data serial input
13
SBSY
I
CD subcode block synchronized signal input
14
SFSY
I
CD subcode frame synchronized signal input
15
SBCK
O
Serial clock output for CD subcode transfer. (Not used. (Open))
16
AVDD
—
Analog (PLL) power supply pin
17
VPRFR
—
VCO oscillation range setting pin
18
VCOC
I
VCO control voltage input
19
VPDO
O
VCO charge pump output
20
AVSS
—
Analog ground
21
DVDD2
—
Power supply pin for internal logic.
22
VSS
—
Ground
23 to 30
MDATA0 to 7
I/O
DRAM data bus 0 to 7
31
DVDD3
—
Digital power supply pin for I/O.
32
VSS
—
Ground
33 to 40
MDATA8 to 15
I/O
DRAM data bus 8 to 15
41
RASB
O
Row Address Strobe signal output (L: active)
42
WEB
O
Data Write Enable signal output (L: active)
43
CASLB
O
Column Address Strobe signal output (for lower byte, L: active)
44
CASUB
O
Column Address Strobe signal output (for upper byte, L: active)
45
OEB
O
Output enable signal output (L: active)
46 to 49
MADRS12 to 9
O
DRAM address output 12 to 9 (Not used. (Open))
50
MADRS8
O
DRAM address output 8
51
DVDD4
—
Digital power supply pin for I/O.
52
VSS
—
Ground
53 to 60
MADRS7 to 0
O
DRAM address output 7 to 0
61
DVDD5
—
Power supply pin for internal logic.
62
VSS
—
Ground
63
STREQ
I/O
MP3 data request flag output (H: active)/DRAM data request flag input (H: active)
(Not used. (Open))
64
STCK
I/O
MP3 data transfer clock input/DRAM data transfer clock output (Not used. (Open))
65
STDAT
I/O
MP3 data serial input/DRAM data serial output (Not used. (Open))
66
FSYNC
O
MP3 frame synchronized signal input (H: active) (Not used. (Open))
67
CRCF
O
CDROM-CRC flag output (H: active)/DRAM data output enable signal output
(H: active) (Not used. (Open))
68
DVDD6
—
Power supply pin for internal logic.
69
VSS
—
Ground
70
WOK
I
DRAM write OK input (at CD-DA, H: active)/DRAM data request flag input
(at CD-ROM, H: active)
SECTION 6
DIAGRAMS
6-1. IC PIN DESCRIPTIONS
• IC1001 LC78683E-US-E (MP3 DECODER, CD-ROM DECODER, ANTI-SHOCK CONTROLLER) (CD BOARD)
Pin No.
Pin Name
I/O
Pin Description
18
CFD-S20CP
Pin No.
Pin Name
I/O
Pin Description
71
CNTOK
O
Data connecting point detection completion flag output (at CD-DA, H: active)/DRAM
data serial output (at CD-ROM, H: active) (Not used. (Open))
72
OVF
O
DRAM write discontinue flag output (at CD-DA, H: active)/DRAM data transfer
clock output (at CD-ROM, H: active) (Not used. (Open))
73
CMDOUT
O
Command serial data output (Nch open drain output pin)
74
CMDIN
I
Command serial data input
75
CL
I
Command serial clock input
76
CE
I
Command enable input (H: active)
77
INTB
O
Interrupt signal output (L: active)
78
RESB
I
System reset input (L: active)
79
DATAIN
I
CD serial data input
80
DATACK
I
CD bit clock input
CFD-S20CP
19
19
68
CMDOUT (MP3)
O
Command serial data output
69
CMDIN (MP3)
I
Command serial data input
70
CL (MP3)
O
Command serial clock output
71
N.C
—
Not used. (Open)
72
DRF (CD)
I
CD focus ON/OFF detection signal input
73
DO (CD)
O
CD data output
74
DI (CD)
I
CD data input
75
CL (CD)
O
CD data transfer clock output
76
CE (CD)
O
CD chip enable output
77
FSEQ (CD)
I
CD synchronized signal detection input
78
RES (CD)
O
CD system reset signal output (L: reset)
79
RESB (MP3)
O
MP3 system reset signal output (L: reset)
80
CE (MP3)
O
MP3 chip enable output
81 to 90
N.C
—
Not used. (Open)
91
A-MUTE
O
Audio muting ON/OFF control signal output
92
MEGA BASS
O
MEGA BASS ON/OFF control signal output
93
P-CON
O
System power control output (H: active)
94
V-DATA
O
Volume data output
95
V-CLOCK
O
Volume clock output
96
N.C
—
Not used. (Open)
97
TAPE PLAY
I
Tape playback switch input (L: playback)
98
REC-IN
I
Tape record signal input (H: record)
99
N.C
—
Not used. (Open)
100
VSS
—
Ground
Pin No.
Pin Name
I/O
Pin Description
6-2. CIRCUIT BOARDS LOCATION
• IC801 µPD784216AGF-527-3BA (SYSTEM CONTROLLER) (MAIN BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
TU-CE
O
PLL chip enable output
2
TU-DATA
O
PLL serial data output
3
TU-CLK
O
PLL serial data transfer clock output
4
TU-COUNT
I
PLL serial count data input
5
TU-MUTE
O
Tuner muting ON/OFF control signal output (L: muting ON)
6
DEST1
I
Destination setting input (Fixed at L: US, Canadian model, H: Singapore, Korean model)
7
DEST2
I
Destination setting input (Fixed at L: US, Canadian model, H: Singapore, Korean model)
8
TEST-B
O
Fixed at L in this set.
9
VDD
—
Power supply pin (+3.3 V)
10
TEST-A
I
Fixed at L in this set.
11
EEPROM-SCL
O
Serial clock output for EEPROM IC (IC802).
12
EEPROM-SDA
I/O
Serial data bus input from/output for EEPROM IC (IC802).
13 to 16
N.C
—
Not used. (Open)
17, 18
ISS1, 2
O
ISS1, 2 output
19
TU-ON
O
Tuner power ON/OFF control signal output (L: power ON)
20
TAPE-ON
O
Tape power ON/OFF control signal output (L: power ON)
21
CD-ON
O
CD power ON/OFF control signal output (L: power ON)
22
TEST/VPP
I
Fixed at L.
23 to 27
N.C
—
Not used. (Open)
28
MP3-LED
O
MP3 LED drive signal output (L: active)
29
LCD-RST
O
LCD system reset signal output (L: reset)
30
LCD-C/D
O
LCD command data output
31
LCD-CS
O
LCD chip select data output
32
LCD-DATA
O
LCD serial data output
33
LCD-CLK
O
LCD clock output
34
N.C
—
Not used. (Open)
35
FM/AM SHIFT
O
Shift point output for oscillation frequency change.
36
N.C
—
Not used. (Open)
37
VDD
—
Power supply pin (+3.3 V)
38
X2
O
System clock output (5 MHz)
39
X1
I
System clock input (5 MHz)
40
VSS
—
Ground
41
XT2
O
Sub clock output (Not used. (Open))
42
XT1
I
Sub clock input (Not used. (Connect to VSS))
43
RESET
I
System reset signal input (L: reset)
44
AC-CHK
I
AC power supply detection signal input (L: AC in)
45
RMC IN
I
Sircs receiver data input
46
WAKE-UP
I
Wake-up input
47
N.C
—
Not used. (Open)
48
CD-DOOR
I
CD lid open/close detection switch input (L: close)
49
INTB (MP3)
I
Interrupt request signal input (L: active)
50
WRQ (CD)
I
CD interruption signal input
51
AVDD
—
Power supply pin (+3.3 V)
52
AVREF0
—
Connect to VDD.
53 to 57
KEY1 to 5
I
Key input 1 to 5
58
REG-CHK
I
REG-CHK detection signal input
59
VH
I
High voltage (+9 V) detection signal input for battery check.
60
VM
I
Middle voltage (+4.5 V) detection signal input for battery check.
61
AVSS
—
Analog ground
62, 63
N.C
—
Not used. (Open)
64
AVREF1
—
Connect to VDD.
65 to 67
N.C
—
Not used. (Open)
CONTROL (4) board
TUNER board
TC board
BATTERY (1) board
BATTERY (2) board
MAIN board
CD board
LCD board
HEADPHONE board
POWER board
CONTROL (2) board
CONTROL (3) board
CONTROL (1) board
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