DOWNLOAD Sony CFD-E95 Service Manual ↓ Size: 3.2 MB | Pages: 61 in PDF or view online for FREE

Model
CFD-E95
Pages
61
Size
3.2 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
cfd-e95.pdf
Date

Sony CFD-E95 Service Manual ▷ View online

37
CFD-E95
– TUNER Board –
IC1
TA2149BN
IC702
BA5826FP-E2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
24
23
22
21
20
19
18
17
16
15
25
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT-DOWN
MONITOR
LEVEL
SHIFT
LEVEL
SHIFT
D.BUFF
D.BUFF
D.BUFF
GND
SLIN
(SLIN)
VREF
VCC
VCC
(FIN)
FIN
F–
F+
SL–
SL+
NC
OPIN
SP–
REG–B
SP+
SPIN
RST
REGO
MUTE
GND
TIN
(TIN)
T–
T+
GND
OPOUT
D.BUFF
D.BUFF
D.BUFF
D.BUFF
D.BUFF
REGULATOR
DRIVER
MUTE
VCC
VCC
RF GND
3
2
1
IF REQ
AM
MIX
FM RFIN
AM LOW CUT
5
4
MIX OUT
VCC
AM IF IN
8
7
6
FM IF IN
GND
10
9
AGC
QUAD
12
11
R-OUT
L-OUT
FM RFOUT
22
23
24
20
21
17
18
19
15
16
13
14
AM RFIN
RF VCC
FM OSC
ST LED
OSC OUT
AM OSC
IF REQ
LPF1
MPX IN
DET OUT
LPF2
FM
MIX
FM
OSC
LEVEL
DET
AM
DET
MUTE
FM
DET
ST/MO
FM/AM
AM
OSC
AGC
SW
ST
1/8
BUFF
BUFF
DIVIDE
DECODE
VCO
IF BUFF
AF BUFF
AF
FM RF
AM IF
FM IF
1/1 OR
1/16
38
CFD-E95
IC2
LC72137M-TLM
– TC Board –
IC301
TA2068N
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
19
20
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
CE
DI
CL
DO
XOUT
AOUT
XIN
AIN
PD
VSS
VDD
B04
FMIN
AMIN
B01
B02
B03
I01
I02
IFIN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
17
18
1
2
3
6
9
10
11
12
8
7
4
5
22
TAPE
TAPE
TAPE
BUF AMP
A1
BUF AMP
A2
NAB
AMP1
NAB
AMP2
23
24
15
14
13
21
20
17
16
RADIO
BUF AMP
B1
BUF AMP
B2
MUTE
MUTE
ON
ON
ON
7dB
26dB
26dB
MONITOR
AMP
LOGIC
18
19
MUTE
7dB
MONITOR
AMP
LINE
TAPE
RADIO
LINE
ALC2
ALC1
DET
REC
AMP1
REC
AMP2
2.1
REF
AMP
MIC
AMP1
LINE
IN1
INT
EXT
RADIO
IN1
REC
PLAY
PRE
OUT1
PRE
OUT2
RADIO
LINE
RADIO
IN2
LINE
IN2
MIC
IN
TAPE
TAPE
VCC
ALC
NAB
OUT1
NAB
NF1
REC
OUT1
NAB
IN1
VREF
GND
NAB
IN2
REC
OUT2
NAB
NF2
NAB
OUT2
MIC
NF
– MAIN Board –
IC302
PT2257-S
1
2
4
8
7
6
5
LIN
SCL
LOUT
VDD
RIN
ROUT
SDA
+

+
3
VSS
CONTROL UNIT
39
CFD-E95
6-19.
IC  PIN  FUNCTION  DESCRIPTION
 MAIN BOARD  IC801  
µ
PD789478GC-A04-8BT (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
NC
Not used
3 to 5
VLC2 to VLC0
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
6 to 9
COM0 to COM3
O
Common drive signal output to the liquid crystal display
10 to 28
SEG0 to SEG18
O
Segment drive signal output to the liquid crystal display
29
REC
I
Recording/playback detection signal input terminal
“L”: playback mode, “H”: recording mode
30
BL-RED
O
LCD back light (red) on/off control signal output terminal    “H”: Red LED on
31
BL-ORG
O
LCD back light (orange) on/off control signal output terminal    “H”: Orange LED on
32
BL-GRN
O
LCD back light (green) on/off control signal output terminal    “H”: Green LED on
33
BL-BLUE
O
LCD back light (blue) on/off control signal output terminal    “H”: Blue LED on
34
LINE
O
Line function control signal output terminal    “H”: line on
35
CD
O
CD function control signal output terminal    “H”: CD on
36
TAPE
O
Tape function control signal output terminal    “H”: tape on
37
ISS2
O
ISS 2 on/off control signal output terminal    “H”: ISS 2 on
38
AVDD
Power supply terminal (+3.3V)
39
AC-CHK
I
AC voltage detection signal input terminal    “L”: AC detected
40
CD DOOR
I
CD lid open/close detection switch input terminal    “L”: CD lid is closed, “H”: CD lid is opened
41
6V-CHK
I
Power supply voltage (+6V) monitor input terminal
42
3V-CHK
I
Power supply voltage (+3V) monitor input terminal
43
9V-CHK
I
Power supply voltage (+9V) monitor input terminal    Not used
44, 45
KEY2, KEY1
I
Front panel key input terminal (A/D input)
46
MODE CHK
I
Model destination setting terminal
47
AGND
Ground terminal
48
RMC
I
Remote control signal input from the remote control receiver
49
TC-PLAY
I
Tape play detection switch input terminal    “L”: tape play mode
50
WP/INI
I/O
Interrupt status input terminal
Output terminal for wake up/Initial reset signal reading
51
JOG-A
I
Jog dial pulse input from the encoder
52
C-WRQ
I
Interruption detection signal input from the digital signal processor
53
C-DOUT
I
Serial data input from the digital signal processor
54
C-DIN
O
Serial data output to the digital signal processor
55
C-CLK
O
Serial data transfer clock signal output to the digital signal processor
56
R-COUNT
I
PLL serial count data input from the FM/AM PLL
57
R-DATA
O
PLL serial data output to the FM/AM PLL
58
R-CLK
O
PLL serial data transfer clock signal output to the FM/AM PLL
59
R-LAT
O
PLL chip enable signal output to the FM/AM PLL
60
R-MUTE
O
Tuner muting on/off control signal output to the FM/AM PLL    “H”: muting on
61
C-DRF
I
Focus on/off detection signal input from the digital signal processor
62
C-CE
O
Chip enable signal output to the digital signal processor
63
C-FSEQ
I
Synchronizing signal detection signal input from the digital signal processor
64
C-XRT
O
System reset signal output to the digital signal processor    “L”: reset
65
P-CON
O
Power on/off control signal output terminal    “L”: standby mode, “H”: power on
66
A-MUTE
O
Audio muting on/off control signal output terminal    “H”: muting on
67
JOG-B
I
Jog dial pulse input from the encoder
68
M-BASS
O
Megabass on/off control signal output terminal    “L”: megabass on
69
IC0
I
Not used
40
CFD-E95
Pin No.
Pin Name
I/O
Description
70
XT1
I
Sub system clock input terminal (32.768 kHz)
71
XT2
O
Sub system clock output terminal (32.768 kHz)
72
VDD
Power supply terminal (+3.3V)
73
VSS
Ground terminal
74
X1
I
Main system clock input terminal (4.19 MHz)
75
X2
O
Main system clock output terminal (4.19 MHz)
76
RST
I
System reset signal input    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
77
V-CLK
O
Serial data transfer clock signal output to the electrical volume
78
V-DATA
O
Serial data output to the electrical volume
79
BL-SLEEP
O
LCD back light sleep control signal output terminal    High Impedance: LCD back light sleep
80
ISS1
O
ISS 1 on/off control signal output    “H”: ISS 1 on
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