Sony CDP-XE200 / CDP-XE300 Service Manual ▷ View online
– 9 –
SECTION 4
DIAGRAMS
4-1. IC PIN FUNCTIONS
• IC101 CXD2545Q (DIGITAL SERVO & DIGITAL SIGNAL PROCESSOR)
• IC101 CXD2545Q (DIGITAL SERVO & DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
SRON
O
Sled drive output (Not used.)
2
SRDR
O
Sled drive output
3
SFON
O
Sled drive output (Not used.)
4
TFDR
O
Tracking drive output
5
TRON
O
Tracking drive output (Not used.)
6
TRDR
O
Tracking drive output
7
TFON
O
Tracking drive output (Not used.)
8
FFDR
O
Focus drive output
9
FRON
O
Focus drive output (Not used.)
10
FRDR
O
Focus drive output
11
FFON
O
Focus drive output (Not used.)
12
VCOO
O
VCO output for analog EFM PLL. (Not used.)
13
VCOI
I
VCO input for analog EFM PLL. (Ground)
14
TEST
I
TEST pin connected normally to Ground.
15
DVSS
—
Digital Ground
16
TES2
I
TEST pin connected normally to Ground.
17
TES3
I
TEST pin connected normally to Ground.
18
PDO
O
Charge-pump output for analog EFM PLL. (Not used.)
19
VPCO
O
Charge-pump output for variable pitch PLL. (Not used.)
20
VCKI
I
Clock input from variable pitch external VCO. (Ground)
21
AVD2
—
Analog power supply
22
IGEN
I
Power supply pin for operational amplifiers.
23
AVS2
—
Analog Ground
24
ADIO
I
(Not used.)
25
RFC
O
(Not used.)
26
RFDC
I
RF signal input
27
TE
I
Tracking error signal input
28
SE
I
Sled error signal input
29
FE
I
Focus error signal input
30
VC
I
Center voltage input pin
31
FILO
O
Filter output for master PLL.
32
FILI
I
Filter input for master PLL.
33
PCO
O
Charge-pump output for master PLL.
34
CLTV
I
Control voltage input for master VCO.
35
AVS1
—
Analog Ground
36
RFAC
I
EFM signal input
37
BIAS
I
Asymmetry circuit constant current input
38
ASYI
I
Asymmetry comparate voltage input
39
ASYO
O
EFM full swing output
40
AVD1
—
Analog power supply
41
DVDD
—
Digital power supply
42
ASYE
I
Asymmetry circuit ON/OFF
43
PSSL
I
Audio data output mode selection input. (Ground)
44
WDCK
O
48-bit slot D/A interface. Word clock
45
LRCK
O
48-bit slot D/A interface. LR clock
46
DATA
O
DA 16 output when PSSL=1. 48-bit slot serial data when PSSL=0.
47
BCLK
O
DA 15 output when PSSL=1. 48-bit slot data when PSSL=0.
– 10 –
Pin No.
Pin Name
I/O
Function
48
64DATA
O
DA 14 output when PSSL=1. 64-bit slot data when PSSL=0. (Not used.)
49
64BCLK
O
DA 13 output when PSSL=1. 64-bit slot data when PSSL=0. (Not used.)
50
64LRCK
O
DA 12 output when PSSL=1. 64-bit slot data when PSSL=0. (Not used.)
51
GTOP
O
DA 11 output when PSSL=1. GTOP output when PSSL=0. (Not used.)
52
XUGF
O
DA 10 output when PSSL=1. XUGF output when PSSL=0. (Not used.)
53
XPLCK
O
DA 09 output when PSSL=1. XPLCK output when PSSL=0.
54
GFS
O
DA 08 output when PSSL=1. GFS output when PSSL=0.
55
PFCK
O
DA 07 output when PSSL=1. RFCK output when PSSL=0.
56
C2PO
O
DA 06 output when PSSL=1. C2PO output when PSSL=0. (Not used.)
57
XRAOF
O
DA 05 output when PSSL=1. XRAOF output when PSSL=0. (Not used.)
58
MNT3
O
DA 04 output when PSSL=1. MNT3 output when PSSL=0.
59
MNT2
O
DA 03 output when PSSL=1. MNT2 output when PSSL=0.
60
MNT1
O
DA 02 output when PSSL=1. MNT1 output when PSSL=0.
61
MNT0
O
DA 01 output when PSSL=1. MNT0 output when PSSL=0.
62
XTAI
I
X’tal oscillator circuit input
63
XTAO
O
X’tal oscillator circuit output (Not used.)
64
XTSL
I
X’tal selection input pin (Ground)
65
DVSS
–
Digital Ground
66
FSTI
I
2/3 divider input of pins 62 and 63.
67
FSTO
O
2/3 divider output of pins 62 and 63.
68
FSOF
O
(Not used.)
69
C16M
O
16.9344MHz output (Not used.)
70
MD2
I
Digital-out ON/OFF control pin (+5V)
71
DOUT
O
Digital-out output pin
72
EMPH
O
Playback disc output in emphasis mode. (Not used.)
73
WFCK
O
WFCK output
74
SCOR
O
Sub-code sync output
75
SBSO
O
Sub-P through Sub-W serial output (Not used.)
76
EXCK
I
Clock input for SBSO read-out. (Ground)
77
SUBQ
O
Sub-Q 80-bit output
78
SQCK
I
Clock input for SQSO read-out.
79
MUTE
I
Muting selection pin
80
SENS
O
SENS output
81
XRST
I
System reset
82
DIRC
I
Used in 1-track jump mode (+5V)
83
SCLK
I
SENS serial data read-out clock
84
DFSW
I
DFCT selection pin (Ground)
85
ATSK
I
Input pin for anti-shock. (Ground)
86
DATA
I
Serial data input, supplied from CPU.
87
XLAT
I
Latch input, supplied from CPU.
88
CLOK
I
Serial data transfer clock input, supplied from CPU.
89
COUT
O
Numbers of track counted signal output. (Not used.)
90
DVDD
–
Digital power supply
91
MIRR
O
Mirror signal output
92
DFCT
O
Defect signal output
93
FOK
O
Focus OK output
94
FSW
O
Output to select spindle motor output filter. (Not used.)
95
MON
O
Output to control ON/OFF of spindle motor. (Not used.)
96
MDP
O
Output to control spindle motor servo
– 11 –
Pin No.
Pin Name
I/O
Function
97
MDS
O
Output to control spindle motor servo. (Not used.)
98
LOCK
O
GFS is sampled by 460Hz. H when GFS is H. (Not used.)
99
SSTP
I
Input signal to detect disc innermost track.
100
SFDR
O
Sled drive output
– 12 –
• IC501 CXP82612-021Q (MASTER CONTROL)
Pin No.
Pin Name
I/O
Function
1
TIMER
–
Connected to +5V.
2
RM
I
Audio bus input
3
+5V
–
Connected to +5V.
4-6
–
–
Not used. (Open)
7
PGML
O
Latch signal output to digital filter (IC201).
8
CLK
O
Serial clock output
9
SENSE
I
SENSE signal input
10
DATA
O
Serial data output
11
SQCK
O
Read out clock output for subcode Q data.
12
SUBQ
I
Subcode Q data input
13
–
–
Not used. (Open)
14
AMUTE
O
Analog muting control signal output
15
LDON
O
Optical pick-up laser diode control output
16
XLT
O
Serial data latch signal output
17
–
–
Not used. (Open)
18
RV+
–
Not used. (Open)
19
RV-
–
Not used. (Open)
20
LDOUT
O
Loading motor control signal output
21
LDIN
I
Loading motor control signal input
22
KEY0
I
Key input (S530)
23
KEY1
I
Key input (S520-S527)
24
KEY2
I
Key input (S501-S506)
25
KEY3
–
Connected to +5V.
26,27
KEY4,KEY5
I
Key input (S531)
28
ADJ/AFADJ
–
ADJ/AFJ test pin
29
IN/OUTSW
I
Loading IN/OUT switch input
30
RST
I
Reset signal input
31
EXTAL
I
Clock input (4MHz)
32
XTAL
O
Clock output (4MHz)
33
VSS
–
Ground
34-41
–
–
Not used. (Open)
42-62
S1-S21
O
FL segment output
63-70
1G-7G
O
FL grid output
71
VFDP(-30V)
–
-30V pin for FL display tube.
72
VDD(+5V)
–
+5V pin
73
+5V
–
+5V pin
74
SEL1
–
Connected to Ground.
75-77
–
–
Connected to Ground.
78
SCOR
I
Read out timing signal input for subcode Q data.
79,80
SEL2,SEL3
–
Connected to +5V.
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