Sony CDP-XB930 / CDP-XB930E Service Manual ▷ View online
25
I
C301 CXD8735N (MAIN BOARD)
6-14. IC BLOCK DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INVI
128FsO
TEST
DINIT
MUTEL
OVFLAG
MUTER
MCKIN
DVSS1
DVDD1
64FSI
NU
XIN
XVSS
AVDDR2
AVSSR2
AVDDR1
64FSO
DVSS2
LVCKO
CKVdd
256FSO
DVDD2
R1(–)
R1(+)
R2(+)
R2(–)
AVSSR2
INVO
BCKI
DATA1
LRCKI
INIT
ATT
SHIFT
LATCH
SYSM
NU
NU
NU
DVSS1
DVDD1
XVDD
AVDDL2
L2(–)
L2(+)
AVSSL2
AVSSL1
L1(+)
L1(–)
AVDDL1
SYNC
VSUB
CKCTL
MUTE
XVDD
S/P
AT
T
MODE
AT
T
REGISTER
D/F
TIMNG
CIRCUIT
“0” DETECT
MUTE
CIRCUIT
1024Fs-CLOCK
BUFFER
Buffer(–)
Buffer(+)
Buffer(+)
Buffer(–)
PLM-R2
PLM-R1
Buffer(–)
Buffer(+)
Buffer(+)
Buffer(–)
PLM-L1
PML-L2
CLOCK
GENERA
TOR
CLOCK
BUFFER
IIR
FIR1
OVERFLOW DETECTER
OR
FIR2
FIR4
FIR3
IIR
ATT
X0.75
FIR1
OVERFLOW DETECTER
FIR2
FIR4
L.I.P
3rd order
NOISE
SHAPER
FIR3
ATT
X0.75
L.I.P
DITHER
3rd order
NOISE
SHAPER
26
IC103 CXA2568M (SERVO BOARD)
IC104 LA6510L (SERVO BOARD)
IC302 CXA8055M (MAIN BOARD)
2
4
9
8
CURRENT
LIMITER
VOUT1
+VIN1
1
VSENCE1
3
–VIN1
7
–VIN2
VCC
10
5
+VIN2
CURRENT
LIMITER
6
VOUT2
VSENCE2
VEE
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP RF_EQ_AMP
ERROR AMP
FOCUS
FOCUS
TRACKING
ERROR AMP
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFO
RFE
FE
TE
(50%/30%
OFF)
OFF)
APC PD AMP
APC LD AMP
42
41
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
24
23
22
32
1
CIREF
ANALOG
VOLUME
CONTROL
CIRCUIT
CONSTANT
CONTROL
CIRCUIT
ECL
SWITCHING
CIRCUIT
ECL
SWITCHING
CIRCUIT
LOGIC
REFERENCE
VOLTAGE
CIRCUIT
NC
AGND
NC
IOR–
IOR+
C5
C6
C7R
AVEES
AVEES
C4R
C3
DVEE
C1R
DGND
1N1–R
1N1+R
NC
1N2+R
1N2–R
RIREF
VREF
VCNT
AGND
AV
CC
NC
IOL–
IOL+
C7L
AVEES
AVEES
C4L
DV
EE
DV
CC
C1L
DGND
1N1–L
1N1+L
NC
1N2+L
1N2–L
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
11
CONSTANT
CONTROL
CIRCUIT
27
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
—
I
I
I
I
I
O
I
I
O
O
O
O
O
O
O
O
—
I/O
I/O
I/O
I/O
I
I/O
O
I
O
—
O
O
O
O
O
O
—
I
I
I
I
I
Description
Digital power supply
System reset “L” : reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Input pin for anti-shock (Connected to GND)
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
4.2336 MHz output (Not used)
Word clock output (f=2fs)
Digital GND
Numbers of track counted signal input/output (Not used)
Mirror signal input/output
Defect signal input/output
Focus OK input/output
Spindle motor external control input (Connected to GND)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor servo
Input signal to detect disc inner most track
2/3 divider output of pin 71
Digital power supply
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital GND
TEST pin connected normally to GND
TEST pin connected normally to GND
Center voltage input pin
Focus error signal input
Sled error signal input
Pin Name
DVDD
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
CM4
WDCK
DVSS
COUT
MIRR
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FSTO
DVDD1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DVSS1
TEST
TES1
VC
FE
SE
• IC 101 DIGITAL SIGNAL PROCESSOR (CXD2585Q) (SERVO board)
• Abbreviation
GFS : Guarded Frame Sync
6-15. IC PIN FUNCTION DESCRIPTION
28
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I
I
I
O
—
I
—
O
I
I
—
I
O
I
O
—
I
I
I/O
O
—
I
I
O
O
O
O
O
I
—
I
O
O
O
O
O
I
I
O
I
Description
Tracking error signal input
Center servo analog input
RF signal input
Test pin (Not used)
Analog GND
Stabilized current input for operation amplifiers
Analog power supply
EFM full swing output
Asymmetry comparate voltage input
EFM signal input
Analog GND
Control voltage input for master VCO1
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Analog power supply
Asymmetry circuit constant current input
VCO2 control voltage input for wide band EFM PLL (Connected to VDD)
VCO2 oscillator input/output for wide band EFM PLL (Not used)
Charge -pump output for wide band EFM PLL (Not used)
Digital power supply
Asymmetry circuit ON/OFF input “ L” : OFF, “H” : ON (Connected to VDD)
Digital-out ON/OFF control input (Connected to VDD)
Digital-out output pin
D/A interface LR clock output (f=Fs)
D/A interface serial data output
D/A interface bit clock output
Playback disc output in emphasis mode (Not used)
X’tal selection input (Connected to ground)
Digital GND
X’tal oscillator circuit input
X’tal oscillator circuit output (Not used)
Serial data output in servo block (Not used)
Serial data read clock output in servo block (Not used)
Serial data latch output in servo block (Not used)
Sub-Q 80-bit and PCM peak level data output (CD text data output)
Clock input for SQSO read-out
Connected to GND
Sub-P through Sub-W serial output (Not used)
Clock input for SBSO read-out (Connected to GND)
Pin Name
TE
CE
RFDC
ADIO
AVSS0
IGEN
AVDD0
ASYO
ASYI
RFAC
AVSS1
CLTV
FILO
FILI
PCO
AVDD1
BIAS
VCTL
V16M
VPCO
DVDD2
ASYE
MD2
DOUT
LRCK
PCMD
BCLK
EMPH
XTSL
DVSS2
XTAI
XTAO
SOUT
SOCK
XOLT
SQSO
SQCK
SCSY
SBSO
EXCK
• Abbreviation
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
PLL : Phase Locked Loop
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