DOWNLOAD Sony CDP-S3 / MHC-S3 Service Manual ↓ Size: 2.13 MB | Pages: 34 in PDF or view online for FREE

Model
CDP-S3 MHC-S3
Pages
34
Size
2.13 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
cdp-s3-mhc-s3.pdf
Date

Sony CDP-S3 / MHC-S3 Service Manual ▷ View online

CDP-S3
21
21
6-9.
SCHEMATIC  DIAGRAM  – PANEL Section –
(Page 19)
D701
D702
D703
D704
D705
R710
R711
R712
R713
R714
R715
R716
R707
R706
R705
R704
R703
R702
R701
R700
S702
S701
S703
S704
S705
S706
S707
S708
CNW703
CN702
CN701
S711
S712
S714
S713
S715
S716
S717
SEL5923A
SEL5423E
SEL5923A
SEL5923A
SEL5923A
270
330
470
560
680
1k
1.2k
1.8k
1.2k
1k
680
560
470
330
270
9P
2P
2P
DISC 3
DISC 1
DISC 2
(DISC 1)
(DISC 3)
(DISC 2)
REPEAT
PLAY MODE
CDP-S3
22
22
• Waveforms
– BD Board –
1
IC101 
ta
 (RFAC) (CD Play mode)
1.1 Vp-p
2
IC101 
ra
 (TE) (CD Play mode)
Approx.
0.4 Vp-p
3
IC101 
el
 (FE) (CD Play mode)
Approx.
0.3 Vp-p
qa
IC401 
qd
 (X-OUT)
2.6 Vp-p
63 ns
4
IC101 
wh
 (MDP)
2.5 Vp-p
7.5 
µ
s
– MAIN Board –
IC102
BA5974FM-E2
• IC Block Diagrams
– BD Board –
IC101
CXD3017Q
TE
RFDC
CE
IGEN 
AVSS0 
ADIO 
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTOR
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
23
CDP-S3
– DRIVER Board –
IC701
BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
O
UT2
O
UT1
RNF
VM
VCC
FIN
GND
RIN
IC103
CXA2581N-T4
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
+
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
DVC
+
+
RW/ROM
VC
RW/ROM
DVC
+
3
A
B
C
D
B
C
A
A
A
B
C
D
B
C D
D
+
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
24
CDP-S3
6-10.
IC  PIN  FUNCTION  DESCRIPTION
 MAIN BOARD  IC401  M30620MAA-B31FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 7
Not used (open)
8
BYTE
I
External data bus line byte selection signal input    “L”: 16 bits, “H”: 8 bits
Not used (fixed at “L”)
9
CNVSS
To flash memory connector
10
Not used (fixed at “L”)
11
Not used (open)
12
RESET
I
Reset signal input from the tuner unit (ST-S3/S5)
13
X-OUT
O
System clock output terminal (16 MHz)
14
VSS
Ground terminal
15
X-IN
I
System clock input terminal (16 MHz)
16
VCC
Power supply terminal (+5V)
17
NMI
I
Non-maskable interrupt input terminal (fixed at “H” in this set)
18
Not used (open)
19
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3017Q (IC101)
20 to 23
Not used (open)
24
BU PWM 3
O
RFDC PWM signal output to the CXA2581N (IC103)
25
Not used (open)
26
BU PWM 2
O
Tracking error PWM signal output to the CXA2581N (IC103)
27
Not used (open)
28
BU PWM 1
O
Focus error PWM signal output to the CXA2581N (IC103)
29
IIC-CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the tuner unit 
(ST-S3/S5)
30
IIC-DATA
I/O
Communication data bus with the tuner system (ST-S3/S5)
31
Not used
32
SQ-DATA-IN
I
Subcode Q data input from the CXD3017Q (IC101)
33
SQ-CLK
O
Subcode Q data reading clock signal output to the CXD3017Q (IC101)
34
RTS1
Not used
35
CD-DATA
O
CD decode data output to the CXD3017Q (IC101)
36
SENS
I
Internal status (SENSE) signal input from the CXD3017Q (IC101)
37
CD-CLK
O
Serial data transfer clock signal output to the CXD3017Q (IC101)
38
CD POWER
O
Power on/off control signal output for the CD mechanism deck section                                             
“L”: standby, “H”: power on
39
Not used (open)
40
HOLD
O
Automatic power control hold signal output to the CXA2581N (IC103)
41
Not used (fixed at “L”)
42
XLT
O
Serial data latch pulse output to the CXD3017Q (IC101)
43
XRST
O
Reset signal output to the CXD3017Q (IC101)
44
LOAD-IN
O
Loading motor drive signal (load-in direction) output the motor driver (IC701)
45
LOAD-OUT
O
Loading motor drive signal (load-out direction) output the motor driver (IC701)
46
OPEN
I
Sub tray load in/out detect switch (S742) input    “L”: sub tray is chucking position
47
CLOSE
I
Sub tray load in/out detect switch (S742) input    “L”: sub tray slides out of chucking position
48
T-SENS1
I
Detection input from the disc tray 1 height sensor (IC731)    
“H”: disc tray 1 position is chucking position
49
T-SENS2
I
Detection input from the disc tray 2 height sensor (IC732)    
“H”: disc tray 2 position is chucking position
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