Sony CDP-M11C / CMT-M11C Service Manual ▷ View online
– 30 –
IC102
BA6397FP
1
2
3
4
7
8
9
10
11
12
13
14
28
27
26
24
22
21
20
19
18
17
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT DOWN
REGULATOR
DRIVER MUTE
LEVEL
SHIFT
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
DRIVE
BUFFER
DRIVE
BUFFER
15
16
23
25
5
6
OUT1A
OUT1B
IN1A
IN1B
TR-B
REG 0
XRST
GND
IN2A
IN2B
OUT2A
OUT2B
GND
OP-OUT
GND
OUT4
A
OUT4
B
IN4A
IN4B
VC
V
CC
V
CC
V
CC
V
CC
IN3B
IN3A
OUT3
B
OUT3
A
OP+
OP–
IC103
CXD2507AQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
52
53
54
55
56
57
58
59
60
61
62
63
64
19
FOK
MON
MDP
MDS
LOCK
TEST
FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
V
SS
WFCK
EMPH
DOUT
C4M
FSTT
XTSL
XTAO
XTAI
MNTO
SERVO AUTO
SEQUENCER
CPU
INTERFACE
DIGITAL
CLV
SUB CODE
PROCESSOR
EFM
DEMODULATOR
DIGITAL
PLL
ASYMMETRY
CORRECTOR
D/A
INTERFACE
ERROR
CORRECTOR
16K
RAM
DIGITAL
OUT
CLOCK
GENERATOR
LRCK
PCMD
BCLK
GTOP
XUGF
XPCK
V
DD
GFS
RFCK
CZPO
XROF
MNT3
MNT1
XLON
SPOD
SPOC
SPOB
SPOA
CLKO
V
DD
XLTO
DATO
CNIN
SEIN
CLOK
XLAT
3
5
14
4
5
3
6
– 31 –
IC104
PCM1710U-B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
28
INPUT
INTERFACE
DIGITAL
FILTER
NOISE
SHAPER
5-LEVEL DAC
RIGHT
LOW-PASS FILTER
RIGHT
3-STAGE AMP
RIGHT
LOW-PASS FILTER
LEFT
3-STAGE AMP
LEFT
5-LEVEL DAC
LEFT
MODE
CONTROL
TIMING
CONTROL
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
V
DD
V
CC
2R
GND2R
EXT1R
EXT2R
VOUTR
GND1
ML/DSD
MC/DM2
MD/DM1
MUTE
MODE
CKSL
DGND
V
DD
V
CC
2L
V
CC
1
GND2L
EXT1L
EXT2L
VOUTL
– MAIN/PANEL/MOTOR Section –
IC101
CXA1291P
1
2
3
6
9
10
16
15
14
11
AMP2
THERMAL SHUT
DOWN AND
CURRENT LIMITER
7
8
AMP1
AMP3
+VIN2
–VIN2
OUT2
OUT1
–VIN1
+VIN1
VEE
VEE
+VIN3
–VIN3
OUT3
NC
NC
VCC
– 32 –
6-5.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC103
µPD78014FGC-532-AB8 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I / O
Function
1
C.SW2
I
Detection input from the chucking address switch (S402)
2
C.SW1
I
Detection input from the chucking address switch (S401)
3
G.SW2
I
Detection input from the gear select switch (S404)
4
G.SW1
I
Detection input from the gear select switch (S403)
5
B.SENS
I
Detection input from the BD vertical position sensor (PH400)
6
B.SW
I
Detection input from the BD bottom switch (S400)
7
T3.SW3
I
Detection input from the disc 3 tray horizontal address switch (S433)
8
T3.SW2
I
Detection input from the disc 3 tray horizontal address switch (S432)
9
VSS
—
Ground terminal
10
T3.SW1
I
Detection input from the disc 3 tray horizontal address switch (S431)
11
T2.SW3
I
Detection input from the disc 2 tray horizontal address switch (S423)
12
T2.SW2
I
Detection input from the disc 2 tray horizontal address switch (S422)
13
T2.SW1
I
Detection input from the disc 2 tray horizontal address switch (S421)
14
T1.SW3
I
Detection input from the disc 1 tray horizontal address switch (S413)
15
T1.SW2
I
Detection input from the disc 1 tray horizontal address switch (S412)
16
T1.SW1
I
Detection input from the disc 1 tray horizontal address switch (S411)
17
BDTEST
I
Setting terminal for BD test mode “L”: test mode, Normally: “H”
18
LED0
O
Drive signal output for the disc 3 pointer LED (D600; green) “L”: LED on
19
LED1
O
Drive signal output for the disc 1 pointer LED (D602; orange) “L”: LED on
20
LED2
O
Drive signal output for the disc 3 pointer LED (D600; orange) “L”: LED on
21
LED3
O
Drive signal output for the disc 1 pointer LED (D602; green) “L”: LED on
22
LED4
O
Drive signal output for the disc 2 pointer LED (D601; green) “L”: LED on
23
LED5
O
Drive signal output for the disc 2 pointer LED (D601; orange) “L”: LED on
24
VSS
—
Ground terminal
25
LED6
O
Drive signal output for the PAUSE LED (D620; orange) “L”: LED on
26
LED7
O
Drive signal output for the PLAY LED (D620; green) “L”: LED on
27
QB-DATA0
I/O
28
QB-DATA1
I/O
29
QB-DATA2
I/O
30
QB-DATA3
I/O
31
BDUP
O
32
BDDOWN
O
33
GEAR
O
34
CHUCK
O
35
RESET
I
System reset signal input from the reset signal generator (IC303) “L”: reset
For several hundreds msec. after the power supply rises, “L” is output, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is output, then it changes to “H”
36
QB-CLK
I
Data transfer clock signal input from the master controller on HMD-M11 (mini-disc deck/tuner/
preamp system)
preamp system)
37
MECHA-POWER
O
Power supply on/off control signal output of the CXA1291P (IC101) “H”: power on
38
QB-READY
I/O
Ready signal in/out terminal with the master controller on HMD-M11 (mini-disc deck/tuner/
preamp system)
preamp system)
39
SCOR
I
Sub-code sync (S0+S1) detection signal input from the CXD2507AQ (IC103)
40
VDD
—
Power supply terminal (+5V)
Two-way data bus with the master controller on HMD-M11 (mini-disc deck/tuner/preamp
system)
system)
BD block up/down motor drive signal output to the CXA1291P (IC101) *1
Chucking/gear motor drive signal output to the CXA1291P (IC101)
– 33 –
Pin No.
Pin Name
I / O
Function
41
X2
O
Main system clock output terminal (10 MHz)
42
X1
I
Main system clock input terminal (10 MHz)
43
IC (VSS)
—
Not used (fixed at “L”)
44
XT2
O
Sub system clock output terminal Not used (fixed at “L”)
45
XT1
I
Sub system clock input terminal Not used (fixed at “L”)
46
AVSS
—
Ground terminal (for A/D converter)
47
KEY0
I
Key input terminal (A/D input) ) + , = 0 , DISC SKIP keys (S601 to S603)
48
KEY1
I
Key input terminal (A/D input) 6 OPEN/CLOSE 1 to 3, ^ , p keys (S621 to S625)
49
FSW
O
Focus gain selection signal output to the CXA1782BQ (IC101)
“H”: normal mode, “L”: focus gain down mode
“H”: normal mode, “L”: focus gain down mode
50
SENS
I
Internal status (SENSE) signal input from the CXD2507AQ (IC103)
51
DFLAT
O
Serial data latch pulse output to the PCM1710U (IC104)
52
BDPWR
O
Power supply on/off control signal output of the BD block “H”: power on
53
LOADOUT
O
54
LOADIN
O
55
AVDD
—
Power supply terminal (+5V) (for A/D converter)
56
AVREF
I
Reference voltage input terminal (+5V) (for A/D converter)
57
SUBQ
I
Sub-code Q data signal input from the CXD2507AQ (IC103)
58
NC
O
Not used (open)
59
SQCLK
O
Sub-code Q data reading clock signal output to the CXD2507AQ (IC103)
60
XRST
O
Reset signal output for the BD block “L”: reset
61
XLAT
O
Serial data latch pulse output to the CXD2507AQ (IC103)
62
NC
I
Not used (fixed at “L”)
63
DATA
O
Serial data output to the CXD2507AQ (IC103) and PCM1710U (IC104)
64
CLK
O
Serial data transfer clock signal output to the CXD2507AQ (IC103) and PCM1710U (IC104)
Loading motor drive signal output to the CXA1291P (IC101) *2
*1 BD block up/down motor control
BDUP (pin #¡)
“L”
“H”
“L”
BDDOWN (pin #™)
“L”
“L”
“H”
Operation
Terminal
OFF
UP
DOWN
*2 Loading motor control
LOADOUT (pin %£)
“L”
“H”
“L”
LOADIN (pin %¢)
“L”
“L”
“H”
Operation
Terminal
OFF
OUT
IN
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