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3.3 V drive voltage (3.5 V for MDS-LSA1 only) is supplied to PHY and LINK from the power supply circuit. PHY starts up when voltage

is supplied to the LPS terminal (Pin 5), while LINK starts when reset is cleared by the H input to the RESET terminal (Pin 85).

When PHY starts, cable bias voltage (1.85 V) is output from the TBIAS2/TBIAS0 terminal (Pins 46/48). The cable bias voltage is output

to TA2N /TA2P/TA0N/TA0P terminals via the buffer (transistor). When the AC power is turned ON/OFF, the transistor goes OFF by the
signal output from the microprocessor, and cable bias is muted to prevent PHY mis-operations.

The master clock of the i.LINK operation circuit is the 24.576 MHz of the crystal oscillator connector to the XO/XI terminal of PHY (Pin

32/33). This clock is divided by 1/2 by PHY, and output to the SYSCLK terminal (Pin 83) of LINK from the SCLK terminal (Pin 8) of PHY.

If PHY and LINK are not started, check the master clock input.

When an external device is connected, and the cable bias voltage is output from the external device to the i.LINK terminal, it is detected

by the TA2N/TA2P/TA0N/TA0P terminals (Pins 51/52/59/60) of PHY, and PHY performs bus reset operations. When an external device is
detected, and the ROOT device is determined by the i.LINK system, the cycle signal (8 kHz/125 µs) which is the sync signal of i.LINK will
be output from ROOT.

When the unit is the ROOT, the cycle signal is generated inside PHY, and output from the TA2N/TA2P/TA0N/TA0P terminals (Pins 51/

52/59/60).

When other devices are not detected, the cycle signal will not be output. Consequently, it will not be output if other devices are not

connected to the unit or when a VAIO PC which has not been turned ON is connected.

The i.LINK signal input from other devices are input as the TB2N and TB2P signals of the i.LINK terminal, or the differential signal of

the TB0N and TB0P. These signals become inversed waveforms.

Packet data is extracted from the input i.LINK signal inside the PHY, and output from the DATA0 to 3 terminals (Pins 13/14/16/17) to

LINK. At this time, the control signal of mutual communication is output or input from or to the CTL0/CTL1 terminal (Pin 10/11) of PHY.

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When other devices are detected by the i.LINK terminal, signals will be output to the DATA0 to 3 terminals of PHY and LINK and CTL0/

1 terminal. If no signal is output to these terminals, check the clock input, power line, etc.

The handling of packet data input to LINK differs according to the data type. The data type of the packet data input is checked. If it is

music data which can be played back, it is sent to the playback circuit. If the data cannot be played back (for image, etc.), it will be ignored.
If it is self-addressed command data (LINC request, etc.), it will be transferred to the microprocessor.

When the i.LINK circuit connected to the AC power supply is started, communication will constantly be performed with the microproces-

sor using the 16 DATA terminals (Pins 38 to 54) of LINK, eight address terminals (Pins 63 to 70), and four control terminals (Pins 57, 58, 59,
and 61).

When stopped

During playback

D3 terminal (LINK Pin 74)...2 V/div, 50 µs

CTL0 terminal (LINK, Pin 80)...2 V/div, 50 µs

When stopped

During playback

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When LINK receives music data which can be played back, it outputs the data to each playback circuit. On the other hand, if music data

is sent to LINK from the playback circuit, it is converted to packet data inside LINK.

1

Input of audio data from CD circuit

Audio data: DATA1 terminal (Pin 15)
Signal clock: BCKI terminal (Pin 13), LRCKI (Pin 14) terminals
Subcode signal: ABSO terminal (Pin 101)
Clock of subcode signal: EXCK terminal (Pin 102), WFCK terminal (Pin 103)
Error status during CD playback: C2PO terminal (Pin 100)

2

Input of audio data from MD circuit

Audio data: DATAI terminal (Pin 15)
Signal clock: BCKI terminal (Pin 13), LRCKI terminal (Pin 14)
Subcode signal: SQSY terminal (Pin 99)
For high speed downloading of ATRAC data: 512FSIN (Pin 2)...preliminary circuit/ Currently not used

Output of audio data to MD circuit

Audio data: DATAO terminal (Pin 22)
Signal clock: BCKO terminal (Pin 20), LRCKO terminal (Pin 21)

3

When the H.A.T.S. circuit is ON, the music signal is stored once in the DRAM, synchronized to internal clock of the unit, read from the

DRAM, and output to the STR circuit. When the H.A.T.S. circuit is OFF, it will be output to the STR circuit immediately.

Audio data input from the STR circuit

Audio data: DIN terminal (Pin 17)

Audio data output to the STR circuit (When H.A.T.S. is OFF)

Audio data: DOUT terminal (Pin 18)
For error flag waveform shaping: EOF terminal (Pin 23)

Audio data input/output with DRAM (When H.A.T.S. is ON)

Audio data: DATA terminal (Pins 127 to 143)
Address signal: Terminal A (Pins 111 to 121)
DRAM control signal: XRAS/XCAS/XOE/XWE terminals (Pins 122 to 125)

Audio data output to STR circuit (When H.A.T.S. is ON)

Audio data: DATA terminal (Pin 22)
Signal clock: 512FSI terminal (Pin 2), BCKO terminal (Pin 20), LRCKO terminal (Pin 21)

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The MDS-LSA1 and STR-LSA1 receives, records or plays sounds from other devices. Consequently, the clocks must be generated

according to the sampling frequency (fs) of the audio signals received. The signal is therefore synchronized by the PLL circuit mounted
externally to LINK.

SYTO terminal (Pin 26) ........... When the i.LINK signal is received, the 1/8 fs clock of the signal received is output.

When fs is 44.1 kHz: 5.51 kHz.

PLLCKI terminal (Pin 27) ........ The 256 fs clock generated in the external PLL circuit is input.

When fs is 44.1 kHz: 11.289 MHz.

1/8OUT terminal (Pin 25) ........ The 1/2048 signal of the signal input to the PLLCKI terminal (Pin 27) is output.

When fs is 44.1 kHz: 5.51 kHz.

When i.LINK audio signal cannot be received, check the SYTO terminal of LINK (Pin 26). If the presence of a clock which is 1/8 times

the sampling frequency can be confirmed at the SYTO terminal, it means that the i.LINK circuit is performing reception operations normally,
and the error is due to malfunction of the digital audio processing circuit after the i.LINK circuit. If the clock cannot be confirmed at the
SYTO terminal, check the signal path between PHY and LINK and the PLL circuit.