Sony CDP-CX50 / CDP-CX571 Service Manual ▷ View online
— 41 —
Pin No.
Pin Name
I/O
Function
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O
O
O
I
I
–
O
–
O
–
–
O
–
O
–
O
I
–
O
O
O
O
I
O
O
I
O
I
I
I
O
O
O
I
I
Deemphasis monitor
The deemphasis disc is being played back when “H”
C2 flag output
Digital OUT output (EIAJ format)
Test input
Incorporates a pull-down resistor
Be sure to connect to 0V
Test input
Incorporates a pull-down resistor
Be sure to connect to 0V
Not used
Be sure to use it in an open state
L channel 1-bit DAC
L channel mute output
L channel 1-bit DAC
L channel power supply
L channel 1-bit DAC
L channel output
L channel 1-bit DAC
L channel ground
Be sure to connect to 0V
R channel 1-bit DAC
R channel ground
Be sure to connect to 0V
R channel 1-bit DAC
R channel output
R channel 1-bit DAC
R channel power supply
R channel 1-bit DAC
R channel mute output
Power supply for the crystal oscillator
Connected to the 16.9344 MHz crystal oscillator
Ground for the crystal oscillator
Be sure to connect to 0V
Sync signal output for the subcode block
C1, C2, single correction, and double correction monitor
Subcode P, Q, R, S, T, U, W output
Subcode frame sync signal output
Rises when the subcode is in a standby
Subcode read clock input
Schmidt input (Connect to 0V when not in use)
7.35 kHz sync signal output divided from the crystal oscillation
Subcode Q output standby output
Read/write control input
Schmidt input
Subcode Q output
Command input from the microprocessor
Command input fetching clock input or subcode extracting clock input from SQOUT
Schmidt input
LC78622 reset input
Temporarily set to “L” when the power is turned ON
Test output
Use it in an open state (Normally, “L” output)
16.9344 MHz output
4.2336 MHz output
Test input. Incorporates a pull-down resistor. Be sure to connect to 0V
Chip select input
Incorporates a pull-down resistor
Be sure to connect to 0V when not in control
Test input
Does not incorporates a pull-down resistor
Be sure to connect to 0V
EMPH
C2F
DOUT
TEST3
TEST4
N. C.
MUTEL
LVDD
LCHO
LVSS
RVSS
RCHO
RVDD
MUTER
XVDD
XOUT
XIN
XVSS
SBSY
EFLG
PW
SFSY
SBCK
FSX
WRQ
RWC
SQOUT
COIN
CQCK
RES
TST11
16M
4.2M
TEST5
CS
TEST1
I
Note) Supply the same potential to each power supply pin (VDD, VVDD, LVDD, RVDD, XVDD).
— 42 —
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
• IC801 SYSTEM CONTROL (CXP82320-074Q)
TSENS1
RMIN
GND
NC
NC
DRF
RWC
CQCK
SQOUT
COIN
TGL
DOOR SW
NC
SL+
SL–
LOAD OUT
LOAD IN
TABLE L
TABLE R
DOWN SW
UP SW
ISENS
DSENS
KEY0
KEY1
KEY2
TEST MODE
JOG1
JOG2
RESET
10MHz
10MHz
GND
PLAY LED
PAUSE LED
PLUS 1 LED
NC
NC
NC
NC
I
I
–
O
O
I
O
O
I
O
I
I
O
O
O
O
O
O
O
I
I
O
I
I
I
O
I
I
I
I
–
–
–
O
O
O
O
O
O
O
Table sensor input
SIRCS input
Ground
Not used
Not used
DRF (FOK) input
RWC (Latch) output
Command output/Clock output for sub code
Sub code reading data input
Command data output
TGL input
DOOR SW input
Not used
Sled motor (External circuit direction) output
Sled motor (Internal circuit direction) output
Loading motor (Out a direction) output
PWM output
Loading motor (In a direction) output
PWM output
Table rotation (Left a direction) output
PWM output
Table rotation (Right a direction) output
PWM output
Loading out SW input
Loading in SW input
Not used
Disc sensor analog input
Operation key (0) analog input
Operation key (1) analog input
Not used
Test mode analg input
Jog dial phase input (1)
Jog dial phase input (2)
Micon reset input
Ceramic oscillator pin
Ceramic oscillator pin
Ground
PLAY LED Output (H: ON)
PAUSE LED Output (H: ON)
PLUS ONE LED Output (H: ON)
Not used
Not used
Not used
Not used
• Abbreviation
TGL : Tracking Gain (Low)
PWM : Pulse Width Modulation
PWM : Pulse Width Modulation
— 43 —
Pin No.
Pin Name
I/O
Function
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
NC
NC
NC
G1
G2
G3
G4
G5
VFDP
VDD
(VDD)
NC
NC
TGC
TEST PULSE
WRQ
TSENS3
TSENS2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
–
–
O
O
O
O
I
I
I
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Fluorescent indicator tube segment output
Not used
Not used
Not used
Fluorescent indicator tube grid output
Fluorescent indicator tube grid output
Fluorescent indicator tube grid output
Fluorescent indicator tube grid output
Fluorescent indicator tube grid output
Reference voltage input for fluorescent indicator tube
+5V power supply
+5V power supply
Not used
Not used
TGL enternal control output
Table position detection pulse output
Sub-code synchronizing signal input
Table sensor (3) input
Table sensor (2) input
— 44 —
7-9. IC BLOCK DIAGRAMS
DEFI
EFLG
SBSY
XVSS
XIN
XOUT
XVDD
MUTER
RVDD
RVDD
RCHO
RVSS
LVSS
LCHO
RVSS
LVSS
LCHO
LVDD
MUTEL
N.C
MUTEL
N.C
TEST4
TAI
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
TEST2
CLV+
CLV-
V / P
HFL
TES
SLICE LEVEL
CONTROL
µ
COM
INTERFACE
XTAL
TIMING GENERATOR
2K x 8BIT
RAM
RAM ADDRESS
GENERATOR
MUTE
SERVO
COMMANDER
CLV
DIGITAL SERVO
DIGITAL
ATTENUATOR
OVERSAMPLING
DIGITAL FILTER
1BIT DAC
L.P.F
DIGITAL OUT
GENERAL PORT
VCO CLOCK OSCILLATION
CLOCK CONTROL
SYNCRONOUS DETECTION
EFM DEMODULATION
SUBCODE CLASSIFICATION
QCRC
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
28
18 19 20 21
23 24 25 26 27
29
30
31
32
63
62
61
60
59 58 57 56 55 54 53 52
51
50
49
48
47
45
46
44
42
43
33
34
41
40
40
39
38
37
36
36
35
22
TEST1
CS
TEST5
RES
TEST1
16M
4.2M
COCK
COIN
SQOUT
RWC
WRQ
FSX
SBCK
SFSY
PW
EMPH
CF2
DOUT
TGL
TOFF
TEST3
JP+
JP-
PCK
FSEQ
VDD
CONT1
CONT2
CONT3
CONT4
CONT5
C1, C2
ERROR DETECTION
&
CORRECTION
FLAG PROTCESS
IC102 LC78622E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
VCC1
LDS
LDD
BHI
PHI
LF2
VR
REFI
VCC2
FSS
DRF
CE
DAT
CL
CLK
DEF
FD-
FA
FA-
FE
FE-
SL-
SL+
AGND
SP
SPI
SPG
SP-
SPD
SLEQ
SLD
JP-
NC
TBC
FSC
DGND
SLI
SLC
RFS-
RFSM
CV+
CV-
CV-
SLOF
HFL
TES
TOFF
TOFF
TGL
JP+
FIN2
FINI
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JR
TO
FD
62
61
60
59
55 54 53 52 51 50
49
48
47
46
45
44
43
41
40
39
38
37
37
36
35
34
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
42
58
57
56
RF DET
I / V
VCA
VCA
LSC
RF AMP
BAL
TE
T. SERVO & T. LOGIC
F. SERVO & F. LOGIC
SPINDLE SERVO
SLED SERVO
µ
-COM
INTERFACE
APC
REF
+ -
+
-
+
-
+
-
+ -
+ -
+ -
- +
+ -
63
IC101 LA9240M
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