Sony CDP-CX240 Service Manual ▷ View online
– 49 –
1
2
3
6
9
10
16
15
14
11
AMP2
THERMAL SHUT
DOWN AND
CURRENT LIMITER
7
8
AMP1
AMP3
+VIN2
–VIN2
OUT2
OUT1
–VIN1
+VIN1
VEE
VEE
+VIN3
–VIN3
OUT3
NC
NC
VCC
• Main (1/2) section
IC503 CXA1291P
ON/OFF
CURRENT
LIMITER
VREF
OVERHEAT
PROTECT
RESET
GENERATOR
ON/OFF
3
6
9
2
5
8
1
4
7
10
ERROR
AMP
ERROR
AMP
VIN1
VO1
CN
EN1
GND
RES
CD
EN2
VO2
VIN2
IC506 LA5616
• Main (2/2) section
24
0
D
R
CK
23
0
D
R
CK
22
0
D
R
CK
21
0
D
R
CK
20
0
D
R
CK
19
0
D
R
CK
18
0
D
R
CK
17
0
D
R
CK
16
0
D
R
CK
15
0
D
R
CK
14
0
D
R
CK
13
4
5
6
7
8
9
10
11
12
0
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
D
1
R
CK
D
1
0
0
R
CK
D
R
CK
D
R
CK
1
2
3
D
1
R
CK
D
1
0
0
R
CK
D
R
CK
D
R
CK
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
QA
QB
VCC
D
ATA
OE
LT
RST
CLK
GND
SQP
QO
QP
IC702 M66310FP
• Display section
– 50 –
6-14. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2587Q)
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
VDD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
VSS
TEST
TES1
XTSL
VC
FE
SE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
O
I
I
I
I
I
I
O
I
–
I/O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
O
–
I
I
I
I
I
I
Sub-Q 80-bit and PCM peak level data output (CD text data output)
Clock input for SQSO read-out
System reset
“L” : reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Digital power supply
Input pin for anti-shock (Connected to ground)
Microcomputer escape interface input A
Microcomputer escape interface input B
Microcomputer escape interface output
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
Numbers of track counted signal input/output (Not used)
Mirror signal input/output (Not used)
Defect signal input/output (Not used)
Focus OK input/output (Not used)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor servo
Input signal to detect disc inner most track
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
X'tal selection input (Connected to ground)
Center voltage input pin
Focus error signal input
Sled error signal input
Pin No.
Pin Name
I/O
Function
• Abbreviation
GFS : Guarded Frame Sync
– 51 –
• Abbreviation
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
PLL : Phase Locked Loop
Pin No.
Pin Name
I/O
Function
TE
CE
RFDC
ADIO
AVSS0
IGEN
AVDD0
ASYO
ASYI
BIAS
RFAC
AVSS3
CLTV
FILO
FILI
PCO
AVDD3
VSS
VDD
DOUT
LRCK
PCMD
BCK
EMPH
XVDD
XTAI
XTAO
XVSS
AVDD1
AOUT1
AIN1
LOUT1
AVSS1
AVSS2
LOUT2
AIN2
AOUT2
AVDD2
RMUT
LMUT
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I
I
I
O
–
I
–
O
I
I
I
–
I
O
I
O
–
–
–
O
O
O
O
O
–
I
O
–
–
O
I
O
–
–
O
I
O
–
O
O
Tracking error signal input
Center servo analog input
RF signal input
Test pin (Not used)
Analog ground
Stabilized current input for operational amplifiers
Analog power supply
EFM full swing output
Asymmetry comparate voltage input
Asymmetry circuit constant current input
EFM signal input
Analog ground
Control voltage input for master VCO1
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Analog power supply
Digital ground
Digital power supply
Digital-out output pin
D/A interface LR clock output (ƒ = Fs) (Not used)
D/A interface serial data output (Not used)
D/A interface bit clock output (Not used)
Playback disc output in emphasis mode (Not used)
Power supply for master clock
X'tal oscillator circuit input (16.9344MHz)
X'tal oscillator circuit output (16.9344MHz)
Ground for master clock
Analog power supply
L-ch analog output
L-ch operational amplifiers input
L-ch line output
Analog ground
Analog ground
R-ch line output
R-ch operational amplifiers input
R-ch analog output
Analog power supply
R-ch “0” detection flag output
L-ch “0” detection flag output
– 52 –
• IC501 SYSTEM CONTROL (CXP84340-094Q)
Pin Name
A3
A4
A5
A6
A7
A12
A14
A11
A10
A9
A8
A13
WE
CE
KBCOUT
KBDOUT
KBDIN
FLDATA
FLCLK
LEDLT
TBLL
TBLR
DRIN
DROUT
ADJ
LDIN
LDOUT
BUSOUT
SMUTE
RST
EXTAL
XTAL
VSS
TX
TEX
AVSS
AVREF
D.S
DOORSW
CD 1/2/3
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
I
O
O
O
O
I
O
O
O
O
I
O
I
–
–
–
–
–
I
O
I
Function
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM address
SRAM writing
SRAM enable
Keyboard clock output
Keyboard data output
Keyboard data input
Data for fluorescent indicator driver IC
Clock for fluorescent indicator driver IC
Latch for LED driver IC
Table motor PWM output for left turn
Table motor PWM output for right turn
Door close output
Door open output
Test mode pin
Loading motor PWM output for inside direction
Loading motor PWM output for outside direction
CONTROL A1 out
Zero mute disenble output
Reset input L: Reset
X'tal Oscillation (10MHz)
X'tal Oscillation (10MHz)
Connect to ground
Not used
Connect to ground
Connect to ground
Connect to +5V
Disc sensor input
Front door switch
Command mode switch
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