Sony CDP-CX200 / CDP-CX205 / CDP-CX225 Service Manual ▷ View online
— 21 —
SECTION 6
DIAGRAMS
6-1. CIRCUIT BOARDS LOCATION
MAIN board
T. SENS board
ILLUMINATION board
DISP board
DOOR SW board
JOG board
RAY-CATCHER board
T. MOTOR board
JACK board
BD board
L. MOTOR board
L.SW board
LUMINOUS board
— 22 —
6-2. IC PIN FUNCTIONS
• IC101 DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR (CXD2545Q)
Pin Name
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
DVss
TES2
TES3
PDO
VPCO
VCKI
AVD2
IGEN
AVS2
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVS1
RFAC
BIAS
ASYI
ASYO
AVD1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
–
I
I
O
O
I
–
I
–
I
O
I
I
I
I
I
O
I
O
I
–
I
I
I
O
–
Function
Sled drive output (Open)
Sled drive output
Sled drive output (Open)
Tracking drive output
Tracking drive output (Open)
Tracking drive output
Tracking drive output (Open)
Focus drive output
Focus drive output (Open)
Focus drive output
Focus drive output (Open)
VCO output for analog EFM PLL (Open)
VCO input from for analog EFM PLL (Connected to Ground)
TEST pin connected normally to Ground (Connected to Ground)
Digital Ground
TEST pin connected normally to Ground
TEST pin connected normally to Ground
Charge-pump output for analog EFM PLL (Open)
Charge-pump output for variable pitch PLL (Open)
Clock input from variable pitch external VCO (Connected to Ground)
Analog power supply
Power supply pin for operational amplifiers
Analog Ground
(Open)
(Open)
RF signal input
Tracking error signal input
Sled error signal input
Focus error signal input
Center voltage input pin
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Control voltage input for master VCO
Analog Ground
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output
Analog power supply
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL: Phase Locked Loop
PLL: Phase Locked Loop
— 23 —
Pin Name
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
GTOP
XUGF
XPLCK
GFS
PFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DVss
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
–
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
–
I
O
O
O
I
O
O
O
O
O
I
O
I
I
O
Function
Digital power supply
Asymmetry circuit ON/OFF (Connected to +5V)
Audio data output mode selection input (Connected to Ground)
48-bit slot D/A interface. Word clock. (Open)
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1.48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1.48-bit slot data when PSSL=0
DA 14 output when PSSL=1.64-bit slot data when PSSL=0 (Open)
DA 13 output when PSSL=1.64-bit slot data when PSSL=0 (Open)
DA 12 output when PSSL=1.64-bit slot data when PSSL=0 (Open)
DA 11 output when PSSL=1.GTOP output when PSSL=0 (Open)
DA 10 output when PSSL=1.XUGF output when PSSL=0 (Open)
DA 09 output when PSSL=1.XPLCK output when PSSL=0 (Open)
DA 08 output when PSSL=1.GFS output when PSSL=0 (Open)
DA 07 output when PSSL=1.RFCK output when PSSL=0 (Open)
DA 06 output when PSSL=1.C2PO output when PSSL=0 (Open)
DA 05 output when PSSL=1.XRA0F output when PSSL=0 (Open)
DA 04 output when PSSL=1.MNT3 output when PSSL=0 (Open)
DA 03 output when PSSL=1.MNT2 output when PSSL=0 (Open)
DA 02 output when PSSL=1.MNT1 output when PSSL=0 (Open)
DA 01 output when PSSL=1.MNT0 output when PSSL=0 (Open)
X'tal oscillator circuit input
X'tal oscillator circuit output (Open)
X'tal selection input pin (Connected to Ground)
Digital Ground
Clock input for digital servo block
2/3 divider output of pins 62, 63
1/4 divider output of pins 62, 63 (Open)
16.9344 MHz output (Open)
Digital-out ON/OFF control pin (Connected to +5V)
Digital-out output pin (Open)
Playback disc output in emphasis mode (Open)
WFCK output (Open)
Sub-code sync output
Sub-P through Sub-W serial output (Open)
Clock input for SBSO read-out (Connected to Ground via a 10 k
Ω
)
Sub-Q 80-bit output
Clock input for SQSO read-out
Muting selection pin
SENS output
• Abbreviation
WFCK: Wirte Frame Clock
— 24 —
Pin Name
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DVDD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I
I
I
I
I
I
I
I
O
–
O
O
O
O
O
O
O
O
I
O
• Abbreviation
GFS: Guard Frame Sync
Function
System reset
Used in 1-track jump mode (Connected to +5v)
SENS serial data read-out clock
Defect selection pin (Connected to Ground)
Input pin for anti-shock (Connected to Ground)
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
Numbers of track counted signal output (Open)
Digital power supply
Mirror signal output (Open)
Defect signal output (Open)
Focus OK output (Open)
Output to select spindle motor output filter (Open)
Output to control ON/OFF of spindle motor (Open)
Output to control spindle motor servo
Output to control spindle motor servo (Open)
GFS is sampled by 460 Hz. H when GFS is H (Open)
Input signal to detect disc inner most track
Sled drive output
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