DOWNLOAD Sony CDP-C591 / CDP-CE235 / CDP-CE335 / SEN-R2900 Service Manual ↓ Size: 2.41 MB | Pages: 28 in PDF or view online for FREE

Model
CDP-C591 CDP-CE235 CDP-CE335 SEN-R2900
Pages
28
Size
2.41 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio / S/M CDP-C591/CE235/CE335 99 US
File
cdp-c591-cdp-ce235-cdp-ce335-sen-r2900.pdf
Date

Sony CDP-C591 / CDP-CE235 / CDP-CE335 / SEN-R2900 Service Manual ▷ View online

— 8 —
SECTION  3
TEST MODE
1
 ADJ Mode
When the main power is turned on while the ADJ terminal is set to
LOW, the CDP-C591/CE235/335 enters the ADJ mode that enables
to implement the servo related checks.
The disk tray is not loaded or rotated.
The fifth program is automatically played back.
The following items are valid even when the main power is turned
on first and the ADJ terminal is then set to LOW.
The high speed search cannot be performed.
The focus servo gain is not decreased.
CLV servo gain is not decreased.
GFS is ignored even if it is set to the LOW.
Q data is ignored even if it cannot be read.
Switching of the monitor terminal is possible.
Every pressing of the FADER key advances the MONITOR
terminal in the following order.
RFCK
nGFCnError rate
When “3” of the remote controller is pressed, the tracking servo
is turned off.
When “8” of the remote controller is pressed, the tracking servo
is turned on.
* The servo related items cannot be checked in the CDP-C591/
CE235/335.
2
 Key Check and Display Check Mode
When the main power is turned on while the AFADJ terminal is set
to LOW, the CDP-C591/CE235/335 enters the key check and display
check mode in which keys and displays can be checked.
First, all display tubes turn on.
When any key is pressed after display tubes are turned on, the
number of the keys that have been pressed appear on the left
and the key number appears on the right.
(Pushing the JOG key is counted as one of the keys.)
However, the following keys are treated as the special keys
that show the different operations.
STOP
: All display turn-on check
PLAY
: Grid check
PAUSE : Segment check
JOG
: Calendar check
When receiving a signal from remote controller, the display
“ []– ** ” appears.
(Number of asterisks ** changes depending on the pressed
key. For example, ** is 50 when the PLAY key is pressed.)
3
 Default Shipment Mode
When the main power is turned on while pressing the DISCSKIP
and the PROGRAM keys, the CDP-C591/CE235/335 enters the
default shipment mode in which the default settings when shipped
from the factory are set.
Move the DISC 1 to the front and stop the machine.  When the
message “NODISC” appears, it indicates that the mode has
ended with success.
4
 Aging Mode
When the OPEN key is pressed while the DISC1 and the CHECK
keys are being pressed with the main power being turned ON, the
CDP-C591/CE235/335 enters the aging mode in which aging is
performed in the following sequence.
Reads TOC
A-1
Accesses the last program
A-2
Plays the last program for 3 seconds
PLAY display appears
EX-CHANGE
A-4
DISCSKIP
A-5
CLOSE
A-6
Accesses the first program
A-7
Playback the first program
PLAY display appears
OPEN
A-9
DISPSKIP
A-A
CLOSE
A-0
When an error occurs during aging, the message “Err–*” appears
and the operation is stopped.
The system does not accept any key operations during aging.
— 9 —
— 10 —
RF PLL Free-run Frequency Check
Procedure :
1.
Connect frequency counter to TP (PLCK) with lead wire.
2.
Turned Power switch on.
3.
Put the disc (YEDS-18) in to play the number five track.
Confirm that reading on frequency counter is 4.3218MHz.
Adjustment Location :
[ BD BOARD ] — Conductor Side —
BD board
TP (PLCK)
frequency counter
TP(VC)
TP(RF)
TP(TE)
TP(TE1)
CN102
TP(FE)
TP(PLCK)
TP(GND)
TP(FE1)
TP(AGCCON)
IC101
20
21
40
41
60
61
80
1
Note :
Clear RF signal waveform means that the shape “ 
 ” can be clearly
distinguished at the center of the waveform.
E-F Balance (1 Track jump) Check
Procedure :
1.
Connect oscilloscope to TP (TE) and TP (VC).
2.
Turned Power switch on.
3.
Load a disc (YEDS-18) and playback the number five track.
4.
Press the  
(  button. (Becomes the 1 track jump mode.)
5.
Confirm that the level B and A (DC voltage) on the oscilloscope
waveform.
Note :
1.
CD Block is basically designed to operate without adjustment.
Therefore, check each item in order given.
2.
Use YEDS-18 disc (3-702-101-01) unless otherwise indicated.
3.
Use an oscilloscope with more than 10M
 impedance.
4.
Clean the object lens by an applicator with neutral detergent
when the signal level is low than specified value with the
following checks.
S-Curve Check
Procedure :
1.
Connect oscilloscope to TP (FE).
2.
Connect between TP (FE1) and TP (VC) by lead wire.
3.
Connect between TP (AGCCON) and TP (GND) by lead wire.
4.
Turn Power switch on.
5.
Load a disc (YEDS-18) and actuate the focus search. (In
consequence of open and close the disc tray, actuate the focus
search)
6.
Confirm that the oscilloscope waveform (S-curve) is
symmetrical between A and B. And confirm peak to peak level
within 4 ±1 Vp-p.
7.
After check, remove the lead wire connected in step 2 and 3.
Note :
• Try to measure several times to make sure than the ratio
of A : B or B : A is more than 10 : 7.
• Take sweep time as long as possible and light up the
brightness to obtain best waveform.
RF Level Check
Procedure :
1.
Connect oscilloscope to TP (RF).
2.
Connect between TP (AGCCON) and TP (GND) by lead wire.
3.
Turned Power switch on.
4.
Load a disc (YEDS-18) and playback.
5.
Confirm that oscilloscope waveform is clear and check RF
signal level is correct or not.
6.
After check, remove the lead wire connected in step 2.
SECTION 4
ELECTRICAL BLOCK CHECKING
BD board
Oscilloscope
TP(FE)
TP(VC)
symmetry
S-curve waveform
within 4 
±
1Vp-p
A
B
TP(RF)
TP(VC)
BD board
oscilloscope
RF signal waveform
VOLT/DIV : 200mV
TIME/DIV : 500ns
level : 1.45 
±
 0.3Vp-p
TP(TE)
TP(VC)
BD board
oscilloscope
level=1.3
±
0.6Vp-p
symmetry
A (DC voltage)
center of
waveform
B
0V
1 track jump waveform
Specified level: –– 
×
 100=less than 
±
22%
B
A
CDP-C591/CE235/CE335
5-1. CIRCUIT BOARDS LOCATION
SECTION  5
DIAGRAMS
BD BOARD
SENSOR BOARD
MAIN BOARD
DISPLAY BOARD
KEY BOARD
POWER SW BOARD
LOADING MOTOR BOARD
TABLE MOTOR BOARD
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this necessary note is printed in
each block)
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted.  pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in 
 and 
1
/
4
 
W or less unless otherwise
specified.
%
: indicates tolerance.
¢
: internal component.
C
: panel designation.
U
: B+ Line.
V
: B– Line.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
• Voltages are taken with a VOM (Input impedance 10 M
).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
J
: CD
c
: CD DIGITAL
• Abbreviation
CND
: Canadian
AED
: North European
AUS
: Aurstrarian
EA
: Saudi Arabia
SP
: Singapore
Note:
The components identi-
fied by mark 
!
 or dotted
line with mark 
!
 are criti-
cal for safety.
Replace only with part
number specified.
Note:
Les composants identifiés par
une marque 
!
 sont critiques
pour la sécurité.
Ne les remplacer que par une
piéce por tant le numéro
spécifié.
— 11 —
— 12 —
Note on Printed Wiring Boards:
• X
: parts extracted from the component side.
¢
: internal component.
• b
: Pattern from the side which enables seeing.
CDP-C591/CE235/CE335
5-2. IC BLOCK DIAGRAMS
BD board
IC101   CXD2587Q
MAIN board
IC304   BA6780
IC603   M5293L
IC601   LA5602
IC103   CXA2568M-T6
— 13 —
— 14 —
TE
RFDC
CE
IGEN 
AVSS0 
ADIO 
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTION
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP       RF_EQ_AMP
ERROR AMP
FOCUS
TRACKING
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFE
FE
TE
(50%/30%
OFF)
APC PD AMP
APC LD AMP
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER 
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
1
2
3
4
5
7
6
V IN
EN
GND
CDEL
CN
RES
V OUT
REFERENCE
VOLTAGE
OVER HEAT
PROTECTION
OVER CURRENT
LIMITTER
ON/OFF
RESET
GEN
ERROR
AMP
2
5
5k
+
27k
OVERCURRENT
LIMITTER
OVERHEAT
PROTECTION
REFERENCE
VOLTAGE
GND
ON/OFF
IN
REFERENCE
VOLTAGE
OUT
3
4
1
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