Sony CDP-C460Z / CDP-CE515 Service Manual ▷ View online
— 27 —
4-9.
IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2545Q)
Pin Name
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
DVss
TES2
TES3
PDO
VPCO
VCKI
AVD2
IGEN
AVS2
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVS1
RFAC
BIAS
ASYI
ASYO
AVD1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
—
I
I
O
O
I
—
I
—
I
O
I
I
I
I
I
O
I
O
I
—
I
I
I
O
—
Function
Sled drive output (Not used)
Sled drive output
Sled drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Focus drive output
Focus drive output (Not used)
Focus drive output
Focus drive output (Not used)
VCO output for analog EFM PLL (Not used)
VCO input for analog EFM PLL (Ground)
TEST pin connected normally to ground
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Charge-pump output for analog EFM PLL (Not used)
Charge-pump output for variable pitch PLL (Not used)
Clock input from variable pitch external VCO (Ground)
Analog power supply
Power supply pin for operational amplifiers
Analog ground
(Not used)
(Not used)
RF signal input
Tracking error signal input
Sled error signal input
Focus error signal input
Center voltage input pin
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Control voltage input for master VCO
Analog ground
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output
Analog power supply
— 28 —
Pin Name
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
GTOP
XUGF
XPLCK
GFS
RFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DVss
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
—
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
—
I
O
O
O
I
O
O
O
O
O
I
O
O
I
O
Function
Digital power supply
Asymmetry circuit ON/OFF
Audio data output mode selection input
48-bit slot D/A interface. Word clock.
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1.48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1.48-bit slot data when PSSL=0
DA 14 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 13 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 12 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 11 output when PSSL=1.GTOP output when PSSL=0 (Not used)
DA 10 output when PSSL=1.XUGF output when PSSL=0 (Not used)
DA 09 output when PSSL=1.XPLCK output when PSSL=0 (Not used)
DA 08 output when PSSL=1.GFS output when PSSL=0 (Not used)
DA 07 output when PSSL=1.RFCK output when PSSL=0 (Not used)
DA 06 output when PSSL=1.C2PO output when PSSL=0 (Not used)
DA 05 output when PSSL=1.XRA0F output when PSSL=0 (Not used)
DA 04 output when PSSL=1.MNT3 output when PSSL=0 (Not used)
DA 03 output when PSSL=1.MNT2 output when PSSL=0 (Not used)
DA 02 output when PSSL=1.MNT1 output when PSSL=0 (Not used)
DA 01 output when PSSL=1.MNT0 output when PSSL=0 (Not used)
X'tal oscillator circuit input
X'tal oscillator circuit output (Not used)
X'tal selection input pin (Ground)
Digital ground
2/3 divider input of pins 62, 63
2/3 divider output of pins 62, 63
(Not used)
16.9344 MHz output (Not used)
Digital-out ON/OFF control pin (+5V)
Digital-out output pin
Playback disc output in emphasis mode (Not used)
WFCK output
Sub-code sync output
Sub-P through Sub-W serial output
Clock input for SBS0 read-out (Ground)
Sub-Q 80-bit output
Sub-code Q clock output
Muting selection pin
SENS output
— 29 —
Pin Name
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DV
DD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I
I
I
I
I
I
I
I
O
—
O
O
O
O
O
O
O
O
I
O
Function
System reset
Used in 1-track jump mode (+5v)
SENS serial data read-out clock
DFCT selection pin (Ground)
Input pin for anti-shock (Ground)
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
Numbers of track counted signal output (Not used)
Digital power supply
Mirror signal output (Not used)
Defect signal output (Not used)
Focus OK output (Not used)
Output to select spindle motor output filter (Not used)
Output to control ON/OFF of spindle motor (Not used)
Output to control spindle motor servo
Output to control spindle motor servo (Not used)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Input signal to detect disc inner most track
Sled drive output
— 30 —
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
I
—
I
—
—
—
—
—
—
—
O
I
I
• IC302 SYSTEM CONTROL (CXP84340-060Q)
Pin Name
D3
D4
D2
D1
D0
A8
A7
A6
A5
A4
A3
A2
A1
PLAY_L
PAUSE_L
MEGA_L
XFADE_
MODELAY_L
WE
LODIN
LODOUT
FLCKL
FLDATA
BLK
A13
A14
NC
D.SENS
NC
RESET
10MHz
10MHz
GND
NC
NC
NC
NC
BUSOUT
VER
KEY6
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Function
SRAM data 3
SRAM data 4
SRAM data 2
SRAM data 1
SRAM data 0
SRAM address 8
SRAM address 7
SRAM address 6
SRAM address 5
SRAM address 4
SRAM address 3
SRAM address 2
SRAM address 1
PLAY lamp
PAUSE lamp
MEGA lamp
XFADE lamp
NO DELAY lamp
SRAM enable
Loading direction signal input
Loading direction signal output
Display clock
Display data
Display reset
SRAM address 13
SRAM address 14
Not used.
Disc exist/non-exist sensor
Not used.
Microprocessor reset
Ceramic oscillator
Ceramic oscillator
Ground (0V)
Not used.
Not used.
Not used.
Not used.
Control A1 output
Model selection
Key input 6
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