DOWNLOAD Sony CDP-C250Z / CDP-C350Z / CDP-C661 / CDP-CE305 / CDP-CE405 Service Manual ↓ Size: 500.16 KB | Pages: 23 in PDF or view online for FREE

Model
CDP-C250Z CDP-C350Z CDP-C661 CDP-CE305 CDP-CE405
Pages
23
Size
500.16 KB
Type
PDF
Document
Service Manual
Brand
Device
Audio / S/M CDP-C250Z/C350Z/ 95/96 US
File
cdp-c250z-cdp-c350z-cdp-c661-cdp-ce305-cdp-ce405.pdf
Date

Sony CDP-C250Z / CDP-C350Z / CDP-C661 / CDP-CE305 / CDP-CE405 Service Manual ▷ View online

— 9 —
RF PLL Free-run Frequency Check
Procedure :
1. Connect frequency counter to test point (PLCK) with lead
wire.
2. Turned Power switch on.
3. Put the disc (YEDS-18) in to play the number five track.
Confirm that reading on frequency counter is 4.3218MHz.
Adjustment Location :
[ BD BOARD ] — Conductor Side —
(PLCK)
(RF)
(VC)
(TE)
(FE)
(FEI)
IC103
1
20
11
10
IC101
[ MAIN BOARD ] — Conductor Side —
40
41
25
24
1
80
65
64
IC401
TP2
(ADJ)
frequency counter
BD board
TP (PLCK)
— 10 —
4-1. CIRCUIT BOARDS LOCATION
SECTION  4
DIAGRAMS
BD BOARD
SENSOR BOARD
MAIN BOARD
DISPLAY BOARD
10 KEY BOARD
LOADING BOARD
TABLE MOTOR BOARD
— 24 —
4-7. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2545Q)
Pin Name
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
DVss
TES2
TES3
PDO
VPCO
VCKI
AVD2
IGEN
AVS2
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVS1
RFAC
BIAS
ASYI
ASYO
AVD1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
I
I
I
O
I
I
I
I
I
O
I
O
I
I
I
I
O
Function
Sled drive output (Not used)
Sled drive output
Sled drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Focus drive output
Focus drive output (Not used)
Focus drive output
Focus drive output (Not used)
VCO output for analog EFM PLL (Not used)
VCO output for analog EFM PLL (GND)
TEST pin connected normally to GND
Digital GND
TEST pin connected normally to GND
TEST pin connected normally to GND
Charge-pump output for analog EFM PLL (Not used)
Charge-pump output for variable pitch PLL (Not used)
Clock input from variable pitch external VCO (GND)
Analog power supply
Power supply pin for operational amplifiers
Analog GND
(Not used)
(Not used)
RF signal input
Tracking error signal input
Sled error signal input
Focus error signal input
Center voltage input pin
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Control voltage input for master VCO
Analog GND
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output
Analog power supply
— 25 —
Pin Name
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
GTOP
XUGF
XPLCK
GFS
PFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DVss
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
I
O
O
O
I
O
O
O
O
O
I
O
I
I
O
Function
Digital power supply
Asymmetry circuit ON/OFF
Audio data output mode selection input
48-bit slot D/A interface. Word clock.
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1.48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1.48-bit slot data when PSSL=0
DA 14 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 13 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 12 output when PSSL=1.64-bit slot data when PSSL=0 (Not used)
DA 11 output when PSSL=1.GTOP output when PSSL=0 (Not used)
DA 10 output when PSSL=1.XUGF output when PSSL=0 (Not used)
DA 09 output when PSSL=1.XPLCK output when PSSL=0
DA 08 output when PSSL=1.GFS output when PSSL=0
DA 07 output when PSSL=1.RFCK output when PSSL=0
DA 06 output when PSSL=1.C2PO output when PSSL=0 (Not used)
DA 05 output when PSSL=1.XRA0F output when PSSL=0
DA 04 output when PSSL=1.MNT3 output when PSSL=0
DA 03 output when PSSL=1.MNT2 output when PSSL=0
DA 02 output when PSSL=1.MNT1 output when PSSL=0
DA 01 output when PSSL=1.MNT0 output when PSSL=0
X'tal oscillator circuit input
X'tal oscillator circuit output (Not used)
X'tal selection input pin (GND)
Digital GND
2/3 divider output of pins 62, 63
2/3 divider output of pins 62, 63
(Not used)
16.9344 MHz output (Not used)
Digital-out ON/OFF control pin (+5V)
Digital-out output pin
Playback disc output in emphasis mode (Not used)
WFCK output
Sub-code sync output
Sub-P through Sub-W serial output (Not used)
Clock input for SBS0 read-out (GND)
Sub-Q 80-bit output
Muting selection pin
SENS output
System reset
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