Sony BDV-IS1000 / BDV-IT1000 / BDV-IT1000ES / HCD-IS1000 / HCD-IT1000 Service Manual ▷ View online
HCD-IS1000/IT1000/IT1000ES
125
Pin No.
Pin Name
I/O
Description
A1
VSS
-
Ground terminal
A2
DVDD
-
Power supply terminal (+3.3V) (for IO)
A3
AFSX0
O
L/R sampling clock signal output to the sample rate converter, HDMI transmitter and stream
processor
processor
A4
ACLKX0
O
Bit clock signal output to the sample rate converter, HDMI transmitter and stream processor
A5
ACLKR0
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
A6
AXR0[14]/AXR2[1]
I
PCM audio signal input from the HDMI receiver
A7
VSS
-
Ground terminal
A8
AXR0[11]/AXR1[2]
I
PCM audio signal input from the A/D converter and HDMI receiver
A9
AXR0[9]/AXR1[4]/
SPI1_SIMO
I/O
Not used
A10
VSS
-
Ground terminal
A11
AXR0[6]/SPI1_ENA#
I/O
Not used
A12 to A14
AXR0[4], AXR0[2],
AXR0[0]
O
PCM audio signal output to the stream processor
A15
DVDD
-
Power supply terminal (+3.3V) (for IO)
A16
VSS
-
Ground terminal
B1
DVDD
-
Power supply terminal (+3.3V) (for IO)
B2
UHPI_HBE[3]#
I
Not used
B3
AHCLKR0/AHCLKR1
I/O
Not used
B4
AFSR0
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
B5, B6
AXR0[15]/AXR2[0],
AXR0[13]/AXR1[0]
I
PCM audio signal input from the HDMI receiver
B7
AXR0[12]/AXR1[1]
I
PCM audio signal input from the A/D converter and HDMI receiver
B8
AXR0[10]/AXR1[3]
I
PCM audio signal input from the digital audio interface receiver
B9
AXR0[8]/AXR1[5]/
SPI1_SOMI
O
PCM audio signal output to the sample rate converter and HDMI transmitter
B10
AXR0[7]/SPI1_CLK
I/O
Not used
B11
AXR0[5]/SPI1_SCS#
I/O
Not used
B12, B13
AXR0[3], AXR0[1]
O
PCM audio signal output to the sample rate converter
B14
SPI0_SOMI
O
Serial data output to the system controller
B15
SPI0_SIMO
I
Serial data input from the system controller
B16
DVDD
-
Power supply terminal (+3.3V) (for IO)
C1
AMUTE0
O
Not used
C2
AHCLKX0/AHCLKX2
I
Master clock signal input from the digital audio interface receiver and HDMI receiver
C3
UHPI_HD[23]
I/O
Not used
C4 to C6
UHPI_HBE[2]# to
HPI_HBE[0]
I
Not used
C7
UHPI_HDS[2]#
I/O
Not used
C8
UHPI_HCS#
I/O
Not used
C9
UHPI_HAS#
I/O
Not used
C10
UHPI_HCNTL[1]
I/O
Not used
C11
AFSX2
I
Error signal input from the digital audio interface receiver, HDMI receiver and HDMI controller
C12
AFSR2
I
PCM audio data input from the digital audio interface receiver and HDMI controller
C13
ACLKR2
I/O
Not used
C14
AHCLKR2
I/O
Not used
C15
SPI0_SCS#
I
Chip select signal input from the system controller
C16
SPI0_CLK
I
Serial data transfer clock signal input from the system controller
D1
AHCLKX1
I/O
Not used
D2
AMUTE1
O
Not used
D3
UHPI_HD[22]
I/O
Not used
D4, D5
DVDD
-
Power supply terminal (+3.3V) (for IO)
D6
UHPI_HRDY#
I
Not used
D7
UHPI_HDS[1]#
I/O
Not used
D8
UHPI_HRW
I
Not used
D9
UHPI_HCNTL[0]
I
Not used
DSP BOARD IC5021 D790E002BZDH300 (DSP)
HCD-IS1000/IT1000/IT1000ES
126
Pin No.
Pin Name
I/O
Description
D10
AMUTE2/HINT#
O
Not used
D11
ACLKX2
O
Interrupt signal output to the system controller
D12, D13
DVDD
-
Power supply terminal (+3.3V) (for IO)
D14
EM_WAIT
I
Not used
D15
EM_OE#
O
Not used
D16
SPI0_ENA#
O
Chip enable signal output to the system controller
E1
ACLKR1
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
E2
ACLKX1
O
Bit clock signal output to the sample rate converter, HDMI transmitter and stream processor
E3
UHPI_HD[21]
I/O
Not used
E4
DVDD
-
Power supply terminal (+3.3V) (for IO)
E5
VSS
-
Ground terminal
E6 to E11
CVDD
-
Power supply terminal (+1.26V) (for core)
E12
VSS
-
Ground terminal
E13
DVDD
-
Power supply terminal (+3.3V) (for IO)
E14
UHPI_HD[8]
I/O
Not used
E15
EM_CS[2]#
O
Not used
E16
EM_RW
O
Not used
F1
AFSR1
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
F2
AFSX1
O
L/R sampling clock signal output to the sample rate converter, HDMI transmitter and stream
processor
processor
F3, F4
UHPI_HD[19],
UHPI_HD[20]
I/O
Not used
F5 to F12
VSS
-
Ground terminal
F13, F14
UHPI_HD[10],
UHPI_HD[9]
I/O
Not used
F15
EM_CS[0]#
O
Chip select signal output to the SD-RAM
F16
EM_RAS#
O
Row address strobe signal output to the SD-RAM
G1
VSS
-
Ground terminal
G2
RESET#
I
Reset signal input from the I/O expander (HD board) "L": reset
G3, G4
UHPI_HD[17],
UHPI_HD[18]
I/O
Not used
G5
CVDD
-
Power supply terminal (+1.26V) (for core)
G6 to G11
VSS
-
Ground terminal
G12
CVDD
-
Power supply terminal (+1.26V) (for core)
G13, G14
UHPI_HD[12],
UHPI_HD[11]
I/O
Not used
G15
EM_BA[0]
O
Bank address signal output to the SD-RAM
G16
VSS
-
Ground terminal
H1
UHPI_HD[16]
I/O
Not used
H2
CLKIN
I
Not used
H3
VSS
-
Ground terminal
H4
UHPI_HD[31]
I/O
Not used
H5
CVDD
-
Power supply terminal (+1.26V) (for core)
H6 to H11
VSS
-
Ground terminal
H12
CVDD
-
Power supply terminal (+1.26V) (for core)
H13, H14
UHPI_HD[14],
UHPI_HD[13]
I/O
Not used
H15
EM_A[10]
O
Address signal output to the SD-RAM
H16
EM_BA[1]
O
Bank address signal output to the SD-RAM
J1
OSCVSS
-
Ground terminal for oscillator
J2
OSCIN
I
System clock input terminal (25 MHz)
J3
OSCOUT
O
System clock output terminal (25 MHz)
J4
OSCVDD
-
Power supply terminal for oscillator
J5
CVDD
-
Power supply terminal (+1.26V) (for core)
J6 to J11
VSS
-
Ground terminal
J12
CVDD
-
Power supply terminal (+1.26V) (for core)
J13
UHPI_HD[15]
I/O
Not used
HCD-IS1000/IT1000/IT1000ES
127
Pin No.
Pin Name
I/O
Description
J14
DVDD
-
Power supply terminal (+3.3V) (for IO)
J15, J16
EM_A[1], EM_A[0]
O
Address signal output to the SD-RAM
K1
VSS
-
Ground terminal
K2
PLLHV
-
Power supply terminal (+3.3V) (for PLL)
K3
TMS
I
Test mode selection signal input terminal (for JTAG)
K4
TRST#
I
Test reset signal input terminal (for JTAG)
K5
CVDD
-
Power supply terminal (+1.26V) (for core)
K6 to K11
VSS
-
Ground terminal
K12
CVDD
-
Power supply terminal (+1.26V) (for core)
K13, K14
UHPI_HD[0],
UHPI_HD[1]
I/O
Not used
K15
EM_A[2]
O
Address signal output to the SD-RAM
K16
VSS
-
Ground terminal
L1
TDI
I
Test data input terminal (for JTAG)
L2 to L4
UHPI_HD[30] to
UHPI_HD[28]
I/O
Not used
L5 to L12
VSS
-
Ground terminal
L13, L14
UHPI_HD[3],
UHPI_HD[4]
I/O
Not used
L15, L16
EM_A[4], EM_A[3]
O
Address signal output to the SD-RAM
M1
EMU[0]#
I/O
Emulation terminal
M2
TDO
O
Test data output terminal (for JTAG)
M3
UHPI_HD[27]
I/O
Not used
M4
DVDD
-
Power supply terminal (+3.3V) (for IO)
M5
VSS
-
Ground terminal
M6 to M11
CVDD
-
Power supply terminal (+1.26V) (for core)
M12
VSS
-
Ground terminal
M13
DVDD
-
Power supply terminal (+3.3V) (for IO)
M14
UHPI_HD[2]
I/O
Not used
M15, M16
EM_A[6], EM_A[5]
O
Address signal output to the SD-RAM
N1
EMU[1]#
I/O
Emulation terminal
N2, N3
UHPI_HD[25],
UHPI_HD[26]
I/O
Not used
N4
EM_D[22]
I/O
Two-way data bus with the SD-RAM
N5
DVDD
-
Power supply terminal (+3.3V) (for IO)
N6 to N11
EM_D[18], EM_D[16],
EM_D[30], EM_D[29],
EM_D[30], EM_D[29],
EM_D[27], EM_D[25]
I/O
Two-way data bus with the SD-RAM
N12
DVDD
-
Power supply terminal (+3.3V) (for IO)
N13, N14
UHPI_HD[5],
UHPI_HD[6]
I/O
Not used
N15, N16
EM_A[8], EM_A[7]
O
Address signal output to the SD-RAM
P1
TCK
I
Test clock signal input terminal (for JTAG)
P2
UHPI_HD[24]
I/O
Not used
P3 to P7
EM_D[21] to EM_D[19],
EM_D[17], EM_D[31]
I/O
Two-way data bus with the SD-RAM
P8
DVDD
-
Power supply terminal (+3.3V) (for IO)
P9 to P11
EM_D[28], EM_D[26],
EM_D[24]
I/O
Two-way data bus with the SD-RAM
P12
EM_A[12]
O
Address signal output terminal Not used
P13
EM_DQM[2]
O
Byte enable signal output to the SD-RAM
P14
UHPI_HD[7]
I/O
Not used
P15
EM_A[11]
O
Address signal output terminal Not used
P16
EM_A[9]
O
Address signal output to the SD-RAM
R1
DVDD
-
Power supply terminal (+3.3V) (for IO)
R2
EM_D[23]
I/O
Two-way data bus with the SD-RAM
R3
EM_CAS#
O
Column address strobe signal output to the SD-RAM
R4
EM_DQM[0]
O
Byte enable signal output to the SD-RAM
HCD-IS1000/IT1000/IT1000ES
128
Pin No.
Pin Name
I/O
Description
R5 to R13
EM_D[6], EM_D[4],
EM_D[2], EM_D[1],
EM_D[2], EM_D[1],
EM_D[15], EM_D[13],
EM_D[12], EM_D[10],
EM_D[12], EM_D[10],
EM_D[8]
I/O
Two-way data bus with the SD-RAM
R14
EM_CLK
O
Clock signal output to the SD-RAM
R15
EM_DQM[3]
O
Byte enable signal output to the SD-RAM
R16
DVDD
-
Power supply terminal (+3.3V) (for IO)
T1
VSS
-
Ground terminal
T2
DVDD
-
Power supply terminal (+3.3V) (for IO)
T3
EM_WE#
O
Write enable signal output to the SD-RAM
T4 to T6
EM_D[7], EM_D[5],
EM_D[3]
I/O
Two-way data bus with the SD-RAM
T7
VSS
-
Ground terminal
T8, T9
EM_D[0], EM_D[14]
I/O
Two-way data bus with the SD-RAM
T10
VSS
-
Ground terminal
T11, T12
EM_D[11], EM_D[9]
I/O
Two-way data bus with the SD-RAM
T13
EM_DQM[1]
O
Byte enable signal output to the SD-RAM
T14
EM_CKE
O
Clock enable signal output to the SD-RAM
T15
DVDD
-
Power supply terminal (+3.3V) (for IO)
T16
VSS
-
Ground terminal
