Sony BDV-HZ970W / BDV-IZ1000W / HBD-HZ970W / HBD-IZ1000W Service Manual ▷ View online
HBD-HZ970W/IZ1000W
97
Pin No.
Pin Name
I/O
Description
BA19
A_RDQ15
I/O
Two-way data bus with the SD-RAM
BA21
A_RCLK0B
O
Clock signal (negative) output to the SD-RAM
BA23
A_RA8
O
Address signal output to the SD-RAM
BA25
A_RA12
O
Address signal output to the SD-RAM
BA27
A_RA7
O
Address signal output to the SD-RAM
BA29
A_RCKE
O
Clock enable signal output to the SD-RAM
BA31
A_RDQ20
I/O
Two-way data bus with the SD-RAM
BA33
A_RDQS2
O
Data strobe signal (positive) output to the SD-RAM
BA35
A_RDQS3B
O
Data strobe signal (negative) output to the SD-RAM
BA37
A_RDQ26
I/O
Two-way data bus with the SD-RAM
BA39
A_RCLK1
O
Clock signal (positive) output to the SD-RAM
BA41
DVSS
-
Ground terminal
BA43
VCC2IO
-
Power supply terminal (+1.8V)
BB2
SRXN_1
I
SATA channel 1 RX differential pair signal (negative) input terminal
BB4
SRXN_2
I
SATA channel 2 RX differential pair signal (negative) input terminal Not used
BB6
SVCTST
-
Not used
BB8
XTAL25MI
I
System clock input terminal (25 MHz)
BB10
TDO
-
Not used
BB12
TDI
-
Not used
BB14
VCC2IO
-
Power supply terminal (+1.8V)
BB16
A_RDQS0B
O
Data strobe signal (negative) output to the SD-RAM
BB18
VCC2IO
-
Power supply terminal (+1.8V)
BB20
A_RDQ10
I/O
Two-way data bus with the SD-RAM
BB22
VCC2IO
-
Power supply terminal (+1.8V)
BB24
A_RRASB
O
Row address strobe signal output to the SD-RAM
BB26
VCC2IO
-
Power supply terminal (+1.8V)
BB28
A_RBA0
O
Bank address signal output to the SD-RAM
BB30
VCC2IO
-
Power supply terminal (+1.8V)
BB32
A_RDQ17
I/O
Two-way data bus with the SD-RAM
BB34
VCC2IO
-
Power supply terminal (+1.8V)
BB36
A_RDQ31
I/O
Two-way data bus with the SD-RAM
BB38
VCC2IO
-
Power supply terminal (+1.8V)
BB40
A_TP_MEMPLL
-
Not used
BB42
VCC2IO
-
Power supply terminal (+1.8V)
BC1
SRXP_1
I
SATA channel 1 RX differential pair signal (positive) input terminal
BC3
STXP_1
O
SATA channel 1 TX differential pair signal (positive) output terminal
BC5
STXP_2
O
SATA channel 2 TX differential pair signal (positive) output terminal Not used
BC7
AVDD33_XTAL25M
-
Power supply terminal (+3.3V)
BC9
GPIO7
-
Not used
BC11
TMS
-
Not used
BC13
A_RDQ2
I/O
Two-way data bus with the SD-RAM
BC15
A_RDQ7
I/O
Two-way data bus with the SD-RAM
BC17
A_RDQS1
O
Data strobe signal (positive) output to the SD-RAM
BC19
A_RDQ13
I/O
Two-way data bus with the SD-RAM
BC21
A_RCLK0
O
Clock signal (positive) output to the SD-RAM
BC23
A_RA0
O
Address signal output to the SD-RAM
BC25
A_RA6
O
Address signal output to the SD-RAM
BC27
A_RA3
O
Address signal output to the SD-RAM
BC29
A_RWEB
O
Write enable signal output to the SD-RAM
BC31
A_RDQ19
I/O
Two-way data bus with the SD-RAM
BC33
A_RDQS2B
O
Data strobe signal (negative) output to the SD-RAM
BC35
A_RDQS3
O
Data strobe signal (positive) output to the SD-RAM
BC37
A_RDQ29
I/O
Two-way data bus with the SD-RAM
BC39
A_RCLK1B
O
Clock signal (negative) output to the SD-RAM
BC41
A_TN_MEMPLL
-
Not used
BC43
A_REXTDN
-
Not used
HBD-HZ970W/IZ1000W
98
MB-135 BOARD IC1201 LAN8700C-AEZG-CTI (ETHERNET INTERFACE)
Pin No.
Pin Name
I/O
Description
1
TX_ER
I
Transmit error signal input from the BD decoder
2
MDC
I
Serial data transfer clock signal input from the BD decoder
3
CRS
O
Carrier sense signal output to the BD decoder
4
MDIO
I/O
Two-way data bus with the BD decoder
5
nRST
I
Reset signal input from the system controller “L”: reset
6
TX_EN
I
Transmit enable signal input from the BD decoder
7
VDD33
-
Power supply terminal (+3.3V)
8
VDD_CORE
-
Power supply terminal (+1.8V) Not used
9 to 12
PA0 to PA3
-
Not used
13
XTAL2
O
System clock output terminal (25 MHz)
14
REFCLK
I
System clock input terminal (25 MHz)
15 to 18
RXD3 to RXD0
O
Receive data output to the BD decoder
19
RX_DV
O
Receive data valid signal output to the BD decoder
20
RX_CLK
O
Receive clock signal output to the BD decoder
21
RX_ER
O
Receive error signal output to the BD decoder
22
TXCLK
O
Transmit clock signal output to the BD decoder
23, 24
TXD0, TXD1
I
Transmit data input from the BD decoder
25
VDDIO
-
Power supply terminal (+3.3V)
26, 27
TXD2, TXD3
I
Transmit data input from the BD decoder
28
TXN
O
Serial data (negative) output to the ethernet connector
29
TXP
O
Serial data (positive) output to the ethernet connector
30
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
31
RXN
I
Serial data (negative) input from the ethernet connector
32
RXP
I
Serial data (positive) input from the ethernet connector
33
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
34
EXRES1
I
Reference resistor connection terminal
35
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
36
COL
O
Collision detect signal output to the BD decoder
HBD-HZ970W/IZ1000W
99
MAIN BOARD IC501 R5F3651MDFC (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VREF
I
Reference voltage (+3.3V) input terminal
2
AVCC
-
Power supply terminal (+3.3V)
3
DIR_HDOUT
I
Serial data input from the digital audio interface receiver
4
DAMP_SCDT/DIR_IN
O
Serial data output to the digital audio interface receiver and stream processor
5
DAMP_SHIFT/
DIR_CLK
O
Serial data transfer clock signal output to the digital audio interface receiver and stream
processor
processor
6
CEC_IN
-
Not used
7
SIRCS_IN
I
SIRCS signal input from the remote control receiver
8
DSP_MOSI
O
Serial data output to the DSP and serial fl ash
9
DSP_MOSO
I
Serial data input from the DSP and serial fl ash
10
DSP_SPICLK
O
Serial data transfer clock signal output to the DSP and serial fl ash
11
BD_PCONT5
O
Power on/off control signal output terminal Not used
12
BD_PCONT6
O
Power on/off control signal output terminal for the BD section “H”: power on
13
BYTE
I
External data bus width selection signal input terminal
14
CNVSS
I
Processor mode selection signal input terminal
15
XCIN
I
Sub system clock input terminal Not used
16
XCOUT
O
Sub system clock output terminal Not used
17
XRESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
18
XOUT
O
Main system clock output terminal (6 MHz)
19
VSS
-
Ground terminal
20
XIN
I
Main system clock input terminal (6 MHz)
21
VCC1
-
Power supply terminal (+3.3V)
22
XNMI/CEC
I/O
CEC serial data input/output with the HDMI ARC OUT connector
23
AC_CUT
I
AC cut detection signal input terminal
24
KEY_INT
I
Key wake-up signal input terminal
25
BD_IF_REQ
I
Request signal input from the BD decoder
26
FL_CS
O
Chip select signal output to the fl uorescent indicator tube driver
27 to 30
NC
-
Not used
31
DIMMER
O
Dimmer control signal output terminal for illumination LED
32
PCONT_FL
O
Power on/off control signal output terminal for the fl uorescent indicator tube “H”: power on
33
CEC_OUT
-
Not used
34
I2C_CLK
I/O
Two-way I2C clock bus terminal Not used
35
I2C_DATA
I/O
Two-way I2C data bus terminal Not used
36
BD_SDI
O
Serial data output to the BD decoder
37
VCC1
-
Power supply terminal (+3.3V)
38
BD_SDO
I
Serial data input from the BD decoder
39
XOUT
O
Main system clock output terminal (6 MHz)
40
BD_SCLK
I
Serial data transfer clock signal input from the BD decoder
41
BD_IF_START
O
Busy request signal output to the BD decoder
42
HDMI_RXD
O
Serial data output to the HDMI controller
43
HDMI_TXD
I
Serial data input from the HDMI controller
44
PCONT1
O
Power on/off control signal output terminal “H”: power on
45
NS_INIT
O
Reset signal output to the stream processor “L”: reset
46
DAMP_SOFT_MUTE
O
Soft muting on/off control signal output to stream processor “L”: muting on
47
FUNC_SEL
O
Function selection signal output terminal
48, 49
DAMP_LATCH2,
DAMP_LATCH1
O
Serial data latch pulse signal output to the stream processor
50, 51
OVERFLOW1,
OVERFLOW2
I
Overfl ow detection signal input from the stream processor
52
DRIVER_RST
O
Reset signal output to the power amplifi er “L”: reset
53
DSP_SPIDS
O
Chip select signal output to the DSP and serial fl ash
54
DSP_SPIENA
I
Enable signal input from the DSP
55
DSP_CS_CTL
O
Hold signal output to the serial fl ash
56
DSP_RESET
O
Reset signal output to the DSP “L”: reset
57
S-AIR_RESET
O
Reset signal output to the sample rate converter and wireless transceiver “L”: reset
58
S-AIR_ADC_SEL
O
Audio data selection signal output terminal for S-AIR section
59
PCONT_S-AIR
O
Power on/off control signal output terminal for the S-AIR section “H”: power on
60
FAN_ON
O
Fan motor on/off control signal output terminal “H”: motor on
HBD-HZ970W/IZ1000W
100
Pin No.
Pin Name
I/O
Description
61
DC_DETECT
I
Speaker DC detection signal input terminal
62, 63
FAN_CONT,
FAN_CONT2
O
Fan motor control signal output terminal
64
DIR_CKST
I
Clock change status input from the digital audio interface receiver
65
FL_DOUT
O
Serial data output to the fl uorescent indicator tube driver
66
NC
-
Not used
67
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube driver
68
ST_DO
I
Serial data input from the tuner (FM)
69
ST_DI
O
Serial data output to the tuner (FM)
70
DIR_RST
O
Reset signal output to the digital audio interface receiver “L”: reset
71
DIR_HCE
O
Chip enable signal output to the digital audio interface receiver
72
DIR_REER
I
Error detection signal input from terminal
73
ANA_DIGI
O
Not used
74
NON_AUDIO
I
Non-PCM or PCM audio data input from terminal
75
MULTI_PCM
O
Multi/PCM data selection signal output terminal
76
NC
-
Not used
77
PCONT2
O
Power on/off control signal output terminal “H”: power on
78 to 80
ASEL_0 to ASEL_2
O
Audio selection signal output terminal
81
NSPMUTE
O
NSP muting on/off control signal output to stream processor
82
EEPROM_SCL
O
I2C clock signal output terminal for the EEPROM
83
EEPROM_SDA
I/O
Two-way I2C data bus terminal for the EEPROM
84
ST_CE
O
Chip enable signal output to the tuner (FM)
85
VCC2
-
Power supply terminal (+3.3V)
86
TUNED
I
Tuned detection signal input from the tuner (FM) “L”: tuned
87
VSS
-
Ground terminal
88
EUP_LVL
-
Not used
89
RDS_DATA
I
RDS serial data input from the tuner (FM) (AEP, Russian and UK models only)
90
RDS_CLK
I
RDS serial data transfer clock signal input from the tuner (FM)
(AEP, Russian and UK models only)
(AEP, Russian and UK models only)
91
DSP_INTR
I
Interrupt signal input from the DSP
92
S-AIR_ID_SW
I
S-AIR ID selection switch input terminal
93
MIC_SW
I
Calibration microphone connection detection signal input terminal
94
MODEL
I
Model setting terminal Not used
95
DESTINATION
I
Destination setting terminal Not used
96
DIR_DATA0
I
Zero data detection signal input from the digital audio interface receiver
97
S-AIR_GPIO2
I
Interrupt signal input from the wireless transceiver
98
DRIVER_SD/
PVDD_DET
I
Shut down signal input from the power amplifi er
99
PCONT3
O
Power on/off control signal output terminal for the HDMI section “H”: power on
100
S-AIR_SDA
I/O
Two-way I2C data bus with the wireless transceiver
101
S-AIR_SCL
O
I2C clock signal output to the wireless transceiver
102
HDMI_RESET
O
Reset signal output to the HDMI controller “L”: reset
103
HDMI_CNVSS
O
Writing mode selection signal output to the HDMI controller “L”: writing mode
104
ST_CLK
O
Serial data transfer clock signal output to the tuner (FM)
105 to
108
NC
-
Not used
109
ACAL_SEL
O
Audio selection signal output terminal
110
CORE_RST
-
Not used
111
CPU_PRERST
O
Reset signal output to the serial fl ash “L”: reset
112
BD_PCONT4
O
Power on/off control signal output terminal Not used
113
OPWRSB
I
Power on/off control signal input from the BD decoder
114
NC
-
Not used
115
FE_EJECT
O
Eject/stop key output to the BD decoder
116
JIG_MODE1
I/O
Two-way mode setting signal bus with the BD decoder
117
UPG_STATUS
I
UPG status signal input from the BD decoder
118
BD_PCONT3
O
Power on/off control signal output terminal for the BD section “H”: power on
119
BD_CS
O
Chip select signal output to the BD decoder
120, 121
BD_PCONT2,
BD_PCONT1,
BD_PCONT1,
O
Power on/off control signal output terminal for the BD section “H”: power on
122
BD_RESET
O
Reset signal output to the BD decoder, NAND fl ash, EEPROM and ethernet interface
123
NC
-
Not used
Ver. 1.1
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