Sony BDV-E500W / HCD-E500W Service Manual ▷ View online
HCD-E500W
77
Pin No.
Pin Name
I/O
Description
E10
IPIDY3
I/O
Not used
E11 to
E13
IPIDC2, IPIDC6,
IPIDC4
I/O
Not used
E14
IPOHSB
I/O
Not used
E15
IPODY7
I/O
Not used
E16, E17
IPODC3, IPODC5
I/O
Not used
E18
SAVDDTIO
-
Power supply terminal (+1.8V)
E19
SAVDDIG
-
Power supply terminal (+1.05V) (digital system)
E20
GPIO32
I/O
Not used
E21
GPIO23
I
Clock signal input terminal (for JTAG) Not used
E22
GPIO31
I/O
Not used
E23
GPIO26
I
Reset signal input terminal (for JTAG) Not used
E24 to
E27
GPIO16, GPIO15,
GPIO2, GPIO1
I/O
Not used
E28
GND
-
Ground terminal
E29
TMODE3
I
Test terminal Not used
E30, E31
AO0BD1, AO0BD2
O
Audio serial data output terminal
E32
AO1BD
O
Not used
E33
AO1MCK
O
Not used
F1
SYSXI
I
System clock signal input terminal (27 MHz)
F2
GND
-
Ground terminal
F3
PCIREQB0
I
Request signal input from the USB interface
F4
PCIIDSEL
I
Initialization device selection signal input from the USB interface
F5
PCICBEB3
I/O
Command and byte enable signal input/output with the USB interface
F6
PCIDEVSELB
I/O
Device selection signal input/output with the USB interface
F7
PCIAD13
I/O
Two-way address and data bus with the USB interface
F8
PCICBEB0
I/O
Command and byte enable signal input/output with the USB interface
F9
PCIAD4
I/O
Two-way address and data bus with the USB interface
F10
IPIDY1
I/O
Not used
F11
IPIDC0
I/O
Not used
F12
IPIDY5
I/O
Not used
F13
IPIDC5
I/O
Not used
F14
IPODY0
I/O
Not used
F15
IPODC1
I/O
Not used
F16
IPODY3
I/O
Not used
F17
SAGNDANA
-
Ground terminal (analog system)
F18
SAVDDTIO
-
Power supply terminal (+1.8V)
F19
SAVDDIG
-
Power supply terminal (+1.05V) (digital system)
F20
GPIO27
I
Debug interrupt signal input terminal (for JTAG) Not used
F21
GPIO30
I
Interrupt signal input from the USB interface
F22
GPIO25
I
Mode selection signal input terminal (for JTAG) Not used
F23
GPIO24
O
Data output terminal (for JTAG) Not used
F24
GPIO17
O
Muting on/off control signal output terminal
F25, F26
GPIO12, GPIO7
I/O
Not used
F27
VRVDD
-
Power supply terminal (+1.05V)
F28
TMODE5
I
Test terminal Not used
F29
TEST
I
Test terminal Not used
F30
S2DOUT
O
Serial data output to the system controller
F31
AO1LRCK
O
Not used
F32
AO1BCK
O
Not used
F33
VDD3
-
Power supply terminal (+3.3V)
G1
SYSXO
O
System clock output terminal (27 MHz)
G2
GND
-
Ground terminal
G3 to G8
PCIAD28, PCIAD26,
PCIAD31, PCIAD15,
PCIAD31, PCIAD15,
PCIAD16, PCIAD10
I/O
Two-way address and data bus with the USB interface
G9
VDD3
-
Power supply terminal (+3.3V)
G10
GND
-
Ground terminal
G11
IPIHSB
I/O
Not used
G12
IPODY4
I/O
Not used
HCD-E500W
78
Pin No.
Pin Name
I/O
Description
G13
IPIDC1
I/O
Not used
G14
VDD3
-
Power supply terminal (+3.3V)
G15
IPODY2
I/O
Not used
G16
SAVDDIG
-
Power supply terminal (+1.05V) (digital system)
G17
SAVDDANA
-
Power supply terminal (+1.8V) (analog system)
G18,
G19
SAGNDDIG
-
Ground terminal (digital system)
G20
GPIO36
I/O
Not used
G21
VDD10
-
Power supply terminal (+1.05V)
G22
GND
-
Ground terminal
G23,
G24
VDD3
-
Power supply terminal (+3.3V)
G25
GPIO11
I/O
Not used
G26
VDD10
-
Power supply terminal (+1.05V)
G27
VRGND
-
Ground terminal
G28
TMODE2
I
Test terminal Not used
G29
S2CKIN
I
Serial data transfer clock signal input from the system controller
G30
S0DOUT
O
Not used
G31
S0CKOUT
O
Not used
G32
S2DIN
I
Serial data input from the system controller
G33
S0DIN
I
Not used
H1
GND
-
Ground terminal
H2
CLKSEL
I
System clock selection signal input terminal
“L”: OSC input, “H”: External clock signal input Fixed at “L” in this set
“L”: OSC input, “H”: External clock signal input Fixed at “L” in this set
H3
PCICLKI
I
33 MHz clock signal input terminal
H4
GND
-
Ground terminal
H5
PCIRSTB
I
Reset signal input from the I/O expander “L”: reset
H6
VDD3
-
Power supply terminal (+3.3V)
H7
VDD10
-
Power supply terminal (+1.05V)
H27, H28
TMODE4, TMODE1
I
Test terminal Not used
H29
S2CSB
I
Chip Select signal input from the system controller
H30
GND
-
Ground terminal
H31
UA1DCDB
I
Not used
H32
UA1RIB
I
Not used
H33
UA1RSTB
O
Not used
J1
UMDQS1
O
Data strobe signal (positive) output to the SD-RAM
J2
GND
-
Ground terminal
J3
UMVDD18
-
Power supply terminal (+1.8V)
J4
CLK27OUT
O
27 MHz clock signal output terminal Not used
J5
PCIAD30
I/O
Two-way address and data bus with the USB interface
J6
VDD3
-
Power supply terminal (+3.3V)
J7
VDD10
-
Power supply terminal (+1.05V)
J27
TMODE0
I
Test terminal Not used
J28
RSTSWB
I
Reset signal input from the I/O expander “L”: reset
J29
UA1DRSB
O
Not used
J30
UA1TXDB
O
Not used
J31
UA1CTSB
O
Not used
J32
UA1DTRB
O
Power supply on/off control signal output terminal for VBUS “H”: power on
J33
UA1RXDB
I
Not used
K1
UMDQSB1
O
Data strobe signal (negative) output to the SD-RAM
K2
GND
-
Ground terminal
K3
UMDQ10
I/O
Two-way data bus with the SD-RAM
K4, K5
GND
-
Ground terminal
K6
UMVDD18
-
Power supply terminal (+1.8V)
K7
GND
-
Ground terminal
K27
NMI
I
Non maskable interrupt signal input terminal Not used
K28
GND
-
Ground terminal
K29
UA0DSRB
I
Busy request signal input from the system controller “L”: busy
K30
UA0CTSB
O
Interlace/progressive selection signal output terminal Not used
K31
UA0DTRB
O
Not used
HCD-E500W
79
Pin No.
Pin Name
I/O
Description
K32
UA0RSTB
O
Not used
K33
UA0RXDB
I
Not used
L1
GND
-
Ground terminal
L2 to L4
UMDQ9, UMDQ12,
UMDQ8
I/O
Two-way data bus with the SD-RAM
L5
UMVDD18
-
Power supply terminal (+1.8V)
L6
GND
-
Ground terminal
L7
UMVDD18
-
Power supply terminal (+1.8V)
L27, L28
SCL1, SCL0
I/O
I2C clock bus terminal Not used
L29
UA0TXDB
O
Not used
L30
UA0DCDB
I
Not used
L31
GND
-
Ground terminal
L32
DVDDYC
-
Power supply terminal (+3.3V) (digital system)
L33
AGNDYC
-
Ground terminal (analog system)
M1
UMCK0
O
Clock signal (positive) output to the SD-RAM
M2
GND
-
Ground terminal
M3, M4
UMDQ13, UMDQ14
I/O
Two-way data bus with the SD-RAM
M5
GND
-
Ground terminal
M6
UMVDD18
-
Power supply terminal (+1.8V)
M7
GND
-
Ground terminal
M27,
M28
SDA1, SDA0
I/O
I2C data bus terminal Not used
M29
UA0RIB
O
Not used
M30
GND
-
Ground terminal
M31
VAY
O
S-video (Y) signal output to the video amplifi er
M32
GND
-
Ground terminal
M33
VAC
O
S-video (chroma) signal output to the video amplifi er
N1
UMCKB0
O
Clock signal (negative) output to the SD-RAM
N2
GND
-
Ground terminal
N3
UMDM1
O
Data mask signal output to the SD-RAM
N4
UMDQ11
I/O
Two-way data bus with the SD-RAM
N5
UMVDD18
-
Power supply terminal (+1.8V)
N6
GND
-
Ground terminal
N7
UMVDD10
-
Power supply terminal (+1.05V)
N13
PLS0VDD
-
Power supply terminal (+1.05V) (for PLL)
N14
PLS0GND
-
Ground terminal (for PLL)
N15
GND
-
Ground terminal
N16
VDD10
-
Power supply terminal (+1.05V)
N17
GND
-
Ground terminal
N18
VDD10
-
Power supply terminal (+1.05V)
N19
GND
-
Ground terminal
N20
PLAUVDD
-
Power supply terminal (+1.05V) (for PLL)
N21
PLA2VDD
-
Power supply terminal (+1.05V) (for PLL)
N27
AVDDYC
-
Power supply terminal (+3.3V) (analog system)
N28
AGNDYC
-
Ground terminal (analog system)
N29
VACOMPYC
-
External capacitor connection terminal
N30
VAREFYC
-
Reference voltage Input terminal
N31 to
N33
GND
-
Ground terminal
P1
GND
-
Ground terminal
P2, P3
UMDQ2, UMDQ15
I/O
Two-way data bus with the SD-RAM
P4
GND
-
Ground terminal
P5
UMVDD18
-
Power supply terminal (+1.8V)
P6
GND
-
Ground terminal
P7
UMVDD10
-
Power supply terminal (+1.05V)
P13
PLSYVDD
-
Power supply terminal (+1.05V) (for PLL)
P14
PLSYGND
-
Ground terminal (for PLL)
P15, P16
GND
-
Ground terminal
P17
VDD10
-
Power supply terminal (+1.05V)
P18, P19
GND
-
Ground terminal
HCD-E500W
80
Pin No.
Pin Name
I/O
Description
P20
PLAUGND
-
Ground terminal (for PLL)
P21
PLA2GND
-
Ground terminal (for PLL)
P27
AVDDYC
-
Power supply terminal (+3.3V) (analog system)
P28
AGNDYC
-
Ground terminal (analog system)
P29
VAR
O
Component video(PR/CR) signal output to the video amplifi er
P30
GND
-
Ground terminal
P31
VAB
O
Component video (PB/CB) signal output to the video amplifi er
P32
GND
-
Ground terminal
P33
VAG
O
Component video (Y) signal output to the video amplifi er
R1
UMDQS0
O
Data strobe signal (positive) output to the SD-RAM
R2
GND
-
Ground terminal
R3, R4
UMDQ1, UMDQ0
I/O
Two-way data bus with the SD-RAM
R5
UMWEB
O
Write enable signal output to the SD-RAM
R6
UMVDD18
-
Power supply terminal (+1.8V)
R7
GND
-
Ground terminal
R13 to
R15
GND
-
Ground terminal
R16
VDD10
-
Power supply terminal (+1.05V)
R17
GND
-
Ground terminal
R18
VDD10
-
Power supply terminal (+1.05V)
R19 to
R21
GND
-
Ground terminal
R27
AVDDRGB
-
Power supply terminal (+3.3V) (analog system)
R28
AGNDRGB
-
Ground terminal (analog system)
R29
VARSETYC
-
External resister connection terminal
R30
VAREFRGB
-
Reference voltage Input terminal
R31
VARSETRGB
-
External resister connection terminal
R32, R33
AGNDH
-
Ground terminal (analog system) (for HDMI)
T1
UMDQSB0
O
Data strobe (negative) output to the SD-RAM
T2
GND
-
Ground terminal
T3, T4
UMDQ4, UMDQ3
I/O
Two-way data bus with the SD-RAM
T5
UMCKERSTB
I
Clock enable control signal input terminal Not used
T6
GND
-
Ground terminal
T7
UMVREF
I
Reference voltage input terminal
T13
VDD10
-
Power supply terminal (+1.05V)
T14
GND
-
Ground terminal
T15
VDD10
-
Power supply terminal (+1.05V)
T16
GND
-
Ground terminal
T17
VDD10
-
Power supply terminal (+1.05V)
T18
GND
-
Ground terminal
T19
VDD10
-
Power supply terminal (+1.05V)
T20
GND
-
Ground terminal
T21
VDD10
-
Power supply terminal (+1.05V)
T27
AVDDRGB
-
Power supply terminal (+3.3V) (analog system)
T28
AGNDRGB
-
Ground terminal (analog system)
T29
VACOMPRGB
-
External capacitor connection terminal
T30
DVDDRGB
-
Power supply terminal (+3.3V) (digital system)
T31
AGNDH
-
Ground terminal (analog system) (for HDMI)
T32
TX2N
O
TMDS data (negative) output to the HDMI connector
T33
TX2P
O
TMDS data (positive) output to the HDMI connector
U1
GND
-
Ground terminal
U2
UMDM0
O
Data mask signal output to the SD-RAM
U3, U4
UMDQ5, UMDQ6
I/O
Two-way data bus with the SD-RAM
U5
UMBA0
O
Bank address signal output to the SD-RAM
U6
UMA10
O
Address signal output to the SD-RAM
U7
GND
-
Ground terminal
U13
GND
-
Ground terminal
U14
VDD10
-
Power supply terminal (+1.05V)
U15
GND
-
Ground terminal
U16
VDD10
-
Power supply terminal (+1.05V)
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