Sony AWP-ZP5 / CX-LZP5 Service Manual ▷ View online
21
CX-LZP5
6-1. IC PIN DESCRIPTION
• IC101 CDX3059AR (CD DSP) (CD BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
MIRR
I/O
Mirror signal input/output (Not used)
2
DFCT
I/O
Defect signal input/output (Not used)
3
FOK
I/O
Focus OK signal input/output (Not used)
4
VSS
—
Internal digital ground
5
LOCK
I/O
GFS is sampled at 460Hz; when GFS is high , this pin outputs a high signal
If GFS is low eight consecutive
6
MDP
O
Spindle motor servo control output
7
SSTP
I
Disk innermost detection signal input
8
IOVSS1
—
I/O digital ground
9
SFDR
O
Sled drive output
10
SRDR
O
Sled drive output
11
TFDR
O
Tracking drive output
12
TRDR
O
Tracking drive output
13
FFDR
O
Focus drive output
14
FRDR
O
Focus drive output
15
IOVDD1
—
I/O digital power supply
16
AVDD0
—
Analog power supply
17
AVSS0
—
Analog ground
18
NC
—
Not used
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input to DSSP block
22
TEO
O
Tracking error signal output from RF amplifier block
23
FEI
I
Focus error signal input to DSSP block
24
FEO
O
Focus error signal output from RF amplifier block
25
VC
I/O
Center voltage output from RF amplifier block
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input
30
NC
—
Not used
31
AVDD4
—
Analog power supply
32
RFDCO
O
RFDC signal output (Not used)
33
PDSENS
I
Reference voltage pin for PD
34
AC_SUM
O
RFAC summing amplifier output
35
EQ_IN
I
Equalizer circuit input
36
LD
O
APC amplifier output
37
PD
I
APC amplifier input
38
NC
—
Not used
39
RFC
I
Equalizer cut-off frequency adjustment pin
40
AVSS4
—
Analog ground
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input or EFM signal input
43
AVDD3
—
Analog power supply
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparator voltage input
46
ASYO
O
EFM full-swing output (Low = VSS, High = VDD)
47
VPCO
O
Wide-band EFM PLL charge pump output
48
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
49
AVSS3
—
Analog ground
50
CLTV
I
Multiplier VCO1 control voltage input
SECTION 6
DIAGRAMS
22
CX-LZP5
Pin No.
Pin Name
I/O
Pin Description
51
FILO
O
Master PLL (slave = digital PLL) filter output
52
FILI
I
Master PLL filter input
53
PCO
O
Master PLL charge pump output
54
AVDD5
—
Analog power supply
55
DDVROUT
O
DC/DC converter output
56
DDVRSEN
I
DC/DC converter output voltage monitor pin
57
AVSS5
—
Analog ground
58
DDCR
I
DC/DC converter reset pin
59
NC
—
Not used
60
BCKI
I
D/A interface bit clock input
61
PCMDI
I
D/A interface serial data input (2’s COMP, MSB first)
62
LRCKl
I
D/A interface LR clock input
63
LRCK
O
D/A interface LR clock output f = Fs
64
VSS
—
Internal digital ground
65
PCMD
O
D/A interface serial data output (2’s COMP, MSB first)
66
BCK
O
D/A interface bit clock output
67
VDD
—
Internal digital power supply
68
EMPH
O
High when the playback disc has emphasis, low it has not
69
EMPHI
I
High when de-emphasis is ON, low when input OFF
70
IOVDD2
—
I/O digital power supply
71
DOUT
O
Digital Out output
72
TEST
I
Test pin Normally ground
73
TEST1
I
Test pin Normally ground
74
IOVSS2
—
I/O digital ground
75
NC
—
Not used
76
XVSS
—
Master clock ground
77
XTAO
O
Crystal oscillation circuit output
78
XTAI
I
Crystal oscillation circuit input
79
XVDD
—
Master clock power supply
80
AVDD1
—
Analog power supply
81
AOUT1
O
Lch analog output
82
VREFL
O
Lch reference voltage
83
AVSS1
—
Analog ground
84
AVSS2
—
Analog ground
85
VREFR
O
Rch reference voltage
86
AOUT2
O
Rch analog output
87
AVDD2
—
Analog power supply
88
NC
—
Not used
89
IOVDD0
—
I/O digital power supply
90
RMUT
O
Rch “0” detection flag (Not used)
91
LMUT
O
Lch “0” detection flag (Not used)
92
NC
—
Not used
93
XTSL
I
Crystal selection input (Not used)
94
IOVSS0
—
I/O digital ground
95
XTACN
I
Oscillation circuit control
Self-oscillation when high, oscillation stop when low
96
SQSO
O
Subcode Q 80-bit and PCM peak and level data output
CD TEXT data output
97
SQCK
I
SQSO readout clock input
98
SBSO
O
Subcode P to W serial output
99
EXCK
I
SBSO readout clock input
100
XRST
I
System reset Reset when low
101
SYSM
I
Mute input Muted when high
23
CX-LZP5
Pin No.
Pin Name
I/O
Pin Description
102
D ATA
I
Serial data input from CPU
103
VSS
—
Internal digital ground
104
XLAT
I
Latch input from CPU The serial data is latched at the falling edge
105
CLOCK
I
Serial data transfer clock input from CPU
106
VDD
—
Internal digital power supply
107
SENS
O
SENS output to CPU
108
SCLK
I
SENS serial data readout clock input
109
ATSK
I/O
Anti-shock input/output
110
WFCK
O
WFCK output (Not used)
111
XUGF
O
XUGF output (Not used)
112
XPCK
O
XPCK output (Not used)
113
GFS
O
GFS output (Not used)
114
C2PO
O
C2PO output (Not used)
115
SCOR
O
High output when the subcode sync, S0 or S1, is detected
116
VDD
—
Internal digital power supply
117
C4M
O
4 2336MHz output (Not used)
118
WDCK
O
Word clock output f = 2Fs (Not used)
119
COUT
I/O
Track number count signal input/output (Not used)
120
NC
—
Not used
24
CX-LZP5
• IC700 M3062CMEN-A18FPU0 (SYSTEM CONTROL) (MAIN BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
O-LCD DATA
O
LCD data output
2
O-LCD SCK
O
LCD clock output
3
O-LCD CS
O
LCD chip select signal output
4
I-RMC
I
Remocon data input
5
O-MP3 DATA
O
MP3 data output
6
I-MP3 DATA
I
MP3 data input
7
O-MP3 CLK
O
MP3 clock output
8
BYTE
—
Ground
9
FLASH
—
Flash write-in mode input pin
10
32kHz IN
I
Clock signal input (32kHz)
11
32kHz OUT
O
Clock signal output (32kHz)
12
I-RESET
I
Reset signal input
13
16MHz OUT
O
Main clock signal output (16MHz)
14
GND
—
Ground
15
16MHz IN
I
Main clock signal input (16MHz)
16
+3.3V
—
Power supply pin (+3.3V)
17
NMI
I
Non maskable interrupt signal input
18
I-RDS CLK
I
RDS clock sinput
19
I-SCOR
I
SCOR signal input
20
I-POWER DOWN
I
AC cut detect signal input
21
O-MP3 STBY
O
MP3 standby signal output
22
I-MP3 REQ
I
MP3 request signal input
23
I-MP3 ACK
I
MP3 acknowledgment signal input
24
O-MILT
O
MP3 latch pulse signal output
25
O-MICS
O
MP3 chip select signal output
26
O-MP3 RST
O
MP3 hardware reset signal output
27
O-XLT
O
CD LAT signal output
28
(NCO)
—
Not used
29
O-SCL
O
I2C clock output
30
O-SDA
O
I2C data output
31
O-DATA
O
CD data output
32
I-SENS
I
SENS signal input
33
O-CLOCK
O
CD clock output
34
O-XRST
O
BD reset signal output
35
O-XTACN
O
Crystal oscillator stop mode signal output
36
O-AMUTE
O
CD mute signal output
37
O-CD ON
O
CD power supply control signal output
38
O-POWER
O
Primary relay control signal output
39
(NCO)
—
Not used
40
I-RDS DATA
I
RDS data input
41
HOLD
O
HOLD signal output
42
I-STEREO
I
FM stereo detect signal input
43
I-TUNE
I
Tuning detect signal input
44
O-PLL CE
O
PLL chip enable signal output
45
O-PLL CLK
O
PLL clock output
46
(NCO)
—
Not used
47
O-PLL DATA
O
PLL data output
48
I-PLL DATA
I
PLL data input
49
O-TU MUTE
O
Tuner mute signal output
50
O-TU ON
O
Tuner power supply control signal output
51
O-LD OUT
O
CD loading motor control signal output
52
O-LD IN
O
CD loading motor control signal output
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