Sharp TU-X1E (serv.man8) Service Manual ▷ View online
TU-X1E/RU
7 – 16
[3] TERMINAL UNIT
1. VHIMM1783CQ-1Q
Pin No.
Pin Name
I/O
Pin Function
1
S1_1
I
S Terminal discrimination connection detection
7
S1_2
I
The discrimination result is outputted to a Status register.
13
S1_3
I
19
S1_4
I
2
Y1
I
Luminance signal input Y1
8
Y2
I
Luminance signal input Y2
14
Y3
I
Luminance signal input Y3
20
Y4
I
Luminance signal input Y4
3
S2_1/FS1
I
S Terminal discrimination aspect ratio information input or SCART terminal FS discrimination
9
S2_2/FS2
I
When using it as FS discrimination, it attenats by the resistance division of 47K+33K.
15
S2_3/FS3
I
21
S2_4/FS4
I
4
C1
I
Chroma signal input C1
10
C2
I
Chroma signal input C2
16
C3
I
Chroma signal input C3
22
C4
I
Chroma signal input C4
5
O1
I
General-purpose output
17
O2
I
It is an open collector type general-purpose output port of the I2C control.
23
O3
I
29
O4
I
6
V2
I
Composite signal input V2
12
V3
I
Composite signal input V3
18
V4
I
Composite signal input V4
24
V5
I
Composite signal input V5
26
V6
I
Composite signal input V6
28
V7
I
Composite signal input V7
100
V1
I
Composite signal input V1
33
VCC9
-
Power-supply voltage 9V
61
72
27
72
27
VCC5
-
Power-supply voltage 9V
66
99
25
99
25
GND
-
Ground
30
40
64
68
80
40
64
68
80
11
BIAS
-
Bias
All the reference voltages used in IC are made based on the resistance division of this terminal.
It is a terminal that puts up the filter capacitor outside for the reference voltage stabilization.
All the reference voltages used in IC are made based on the resistance division of this terminal.
It is a terminal that puts up the filter capacitor outside for the reference voltage stabilization.
76
ADR
I
Slave address setting
Slave address 90H and 92H can be selected according to the voltage applied to this terminal.
It is set to 90H by Low, and is set to 92H by High.
Slave address 90H and 92H can be selected according to the voltage applied to this terminal.
It is set to 90H by Low, and is set to 92H by High.
31
SCL
I
I2C BUS clock input
32
SDA
I/O
I2C BUS data input/output
41-60
L1-L10
R1-R10
R1-R10
I
Audio line input
It equips it with ten systems.
It equips it with ten systems.
34-39
LOUT1-3
ROUT1-3
ROUT1-3
O
Audio line output
0dB/6dB of the voltage gain is selected by the control register.
0dB/6dB of the voltage gain is selected by the control register.
62
DCOUT
O
DC output terminal for S terminal
65
VOUT3
O
Monitor output terminal (composite)
63
COUT3/
VOUT6
VOUT6
O
Monitor output terminal (Chroma or composite)
67
VOUT3/
VOUT5
VOUT5
O
Monitor output terminal (Luminance or composite)
69
PROUT2
O
Color difference Pr signal output terminal 2
70
PBOUT2/
COUT2
COUT2
O
Color difference Pb signal output terminal 2
TU-X1E/RU
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2. VHIAK4384ET-1Y 24bit-DAC
71
CYOUT2
/YOUT2
/VOUT2
/YOUT2
/VOUT2
O
It is color difference CY signal output or brightness output or composite output terminal2.
73
PROUT1
O
Color difference Pr signal output terminal 1
It is possible to switch in the D5 mode and the D4 mode.
It is possible to switch in the D5 mode and the D4 mode.
74
PBOUT1
/COUT1
/COUT1
O
Color difference Pb signal output terminal 1
It is possible to switch in the D5 mode and the D4 mode.
It is possible to switch in the D5 mode and the D4 mode.
75
CYOUT1
/YOUT1
/VOUT1
/YOUT1
/VOUT1
O
It is color difference CY signal output or brightness output or composite output terminal1.
77
78
79
78
79
SW3
SW2
SW1
SW2
SW1
I
D Terminal discrimination connection detection signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
81
87
93
87
93
DL1_1
DL1_2
DL1_3
DL1_2
DL1_3
I
D Terminal discrimination number of scanning lines information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
82
88
94
88
94
CY1
CY2
CY3
CY2
CY3
I
Component Y signal input
83
89
95
89
95
DL2_1
DL2_2
DL2_3
DL2_2
DL2_3
I
D Terminal discrimination I/P information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
84
90
96
90
96
PB1
PB1
PB1
PB1
PB1
I
Color-difference signal PB input
RGB signal can also be inputted.
RGB signal can also be inputted.
85
91
97
91
97
DL3_1
DL3_2
DL3_3
DL3_2
DL3_3
I
D Terminal discrimination aspect ratio information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
86
92
98
92
98
PR1
PR2
PR3
PR2
PR3
I
Color-difference signal PR input
RGB signal can also be inputted.
RGB signal can also be inputted.
Pin No.
Pin Name
I/O
Pin Function
1
MCLK
I
Master Clock input pin.
An external TTL clock should be input on this pin.
An external TTL clock should be input on this pin.
2
BICK
I
Audio serial data clock pin.
3
SDTI
I
Audio serial data input pin.
4
LRCK
I
L/R clock pin.
5
PDN
I
Power-Down mode pin.
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
6
SMUTE CSN
I
Soft mute pin in parallel mode
"H": Enable, "L" : Disable
Chip select pin in serial mode.
"H": Enable, "L" : Disable
Chip select pin in serial mode.
7
ACKS CCLK
I
Auto setting mode pin in parallel mode.
"L": manual setting mode. "H": auto setting mode.
Control data clock pin in serial mode.
"L": manual setting mode. "H": auto setting mode.
Control data clock pin in serial mode.
8
DID0 CDTI
I
Audio data interface format pin in parallel mode.
Control data input pin in serial mode.
Control data input pin in serial mode.
9
P/S
I
Parallel/Serial select pin.
"L": serial control mode.. "H": Parallel control mode.
"L": serial control mode.. "H": Parallel control mode.
10
AOUTR
O
Rch analog output pin.
11
AOUTL
O
Lch analog output pin.
12
VCOM
O
Common voltage pin, VDD/2
Nominally connected to VSS with a 0.1
Nominally connected to VSS with a 0.1
µF ceramic capacitor in parallel with a 10µF electrolytic cap.
13
VSS
-
Ground pin.
14
VDD
-
Power supply pin.
15
DZFR
O
Rch data zero input detect pin.
16
DZFL
O
Lch data zero input detect pin.
Pin No.
Pin Name
I/O
Pin Function
TU-X1E/RU
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3. VHIAK4683EQ-1Q (ASSY: IC1404) Asynchronous Multi-Channel Audio CODEC with DIR/T.
Pin No.
Pin Name
I/O
Pin Function
1
PVDD
---
PLL Power supply, 4.5V - 5.5V.
2
RX0
I
Receiver Channel 0 (Internal biased pin. Internally biased at PVDD/2).
3
I2C
I
Control Mode Select.
"L”: 4-wire Serial "H”: I2C Bus
"L”: 4-wire Serial "H”: I2C Bus
4
RX1
I
Receiver Channel 1.
5
RX2
I
Receiver Channel 2.
6
RX3
I
Receiver Channel 3.
7
INT
O
Interrupt
8
DZF
O
Zero Input Detect.
When the input data of DAC follow total 8192 LRCK cycles with “0”input data, this pin goes to “H”. And when
RSTN1 bit is “0”, PWDA bit is “0”, this pin goes to "H”
When the input data of DAC follow total 8192 LRCK cycles with “0”input data, this pin goes to “H”. And when
RSTN1 bit is “0”, PWDA bit is “0”, this pin goes to "H”
9
CDTO
O
Control Data Output in Serial Mode and I2C pin="L”.
10
LRCKB
I/O
Channel Clock B
11
BICKB
I/O
Audio Serial Data Clock B
12
SDTOB
O
Audio Serial Data Output B
13
OLRCKA
I/O
Output Channel Clock A
14
ILRCKA
I/O
Input Channel Clock A
15
BICKA
I/O
Audio Serial Data Clock A
16
SDTOA
O
Audio Serial Data Output A
17
MCKO
O
Master Clock Output
18
TVDD
---
Output Buffer Power Supply, 2.7V - 5.5V
19
DVSS
---
Digital Ground
20
DVDD
---
Digital Power Supply, 4.5V - 5.5V
21
XTI
I
X'tal Input
22
XTO
O
X'tal Output
23
TX
O
Transmit Channel Output
When DIT bit="0”, RX0 - 3 Through.
When DIT bit="1”, Internal DIT Output.
When DIT bit="0”, RX0 - 3 Through.
When DIT bit="1”, Internal DIT Output.
24
MCLK2
I
Master Clock Input
25
PDN
I
Power-Down Mode and Reset
When"L”, the AK4683 is powered-down, all registers are reset. And then all digital output pins go "L”. The
AK4683 must be reset once upon power-up.
When"L”, the AK4683 is powered-down, all registers are reset. And then all digital output pins go "L”. The
AK4683 must be reset once upon power-up.
26
SDA
I/O
Control Data in Serial Mode and I2C pin="H”.
27
SCL
I
Control Data Clock in Serial Mode and I2C pin="H”
28
CSN
I
Chip Select in Serial Mode and I2C pin="L”.
29
SDTIA1
I
Audio Serial Data Input A1
30
SDTIA2
I
Audio Serial Data Input A2
31
SDTIA3
I
Audio Serial Data Input A3
32
SDTIB
I
Audio Serial Data Input B
33
HVDD
---
HP Power Supply, 4.5V - 5.5V
34
HVSS
---
HP Ground
35
HPR
O
HP Rch Output.
36
HPL
O
HP Lch Output.
37
MUTET
---
HP Common Voltage Output
38
LOUT2
O
DAC2 Lch Positive Analog Output
39
ROUT2
O
DAC2 Rch Positive Analog Output
40
LOUT1
O
DAC1 Lch Positive Analog Output
41
ROUT1
O
DAC1 Rch Positive Analog Output
42
VCOM
---
DAC/ADC Common Voltage Output
43
AVDD2
---
DAC Power Supply, 4.5V - 5.5V
44
AVSS2
---
DAC Ground
45
LISEL
O
Lch Feedback Resistor Output
46
LOPIN
O
Lch Feedback Resistor Input. 0.5 x AVDD1.
47
ROPIN
O
Rch Feedback Resistor Input. 0.5 x AVDD1.
48
RISEL
O
Rch Feedback Resistor Output
49
AVSS1
---
ADC Ground
50
AVDD1
---
ADC Power Supply, 4.5V - 5.5V
51
LIN1
I
Lch Input 1
52
RIN1
I
Rch Input 1
53
LIN2
I
Lch Input 2
54
RIN2
I
Rch Input 2
55
LIN3
I
Lch Input 3
56
RIN3
I
Rch Input 3
TU-X1E/RU
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57
LIN4
I
Lch Input 4
58
RIN4
I
Rch Input 4
59
LIN5
I
Lch Input 5
60
RIN5
I
Rch Input 5
61
LIN6
I
Lch Input 6
62
RIN6
I
Rch Input 6
63
PVSS
---
PLL Ground
64
R
---
External Resistor
Pin No.
Pin Name
I/O
Pin Function
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