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Model
TU-X1E (serv.man8)
Pages
22
Size
1.01 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
tu-x1e-sm8.pdf
Date

Sharp TU-X1E (serv.man8) Service Manual ▷ View online

TU-X1E/RU
7 – 11
7. VHIS29GL256-1Q   256Mbit Flash Memory
Pin No.
Pin Name
I/O
Pin Function
1
A23
I
24 Address inputs (256Mb)
1
A23
I
2
A22
I
15
A21
I
12
A20
I
11
A19
I
18
A18
I
19
A17
I
54
A16
I
3
A15
I
4
A14
I
5
A13
I
6
A12
I
7
A11
I
8
A10
I
9
A9
I
10
A8
I
20
A7
I
21
A6
I
22
A5
I
23
A4
I
24
A3
I
25
A2
I
26
A1
I
31
A0
I
51
DQ15/A-1
I/O
DQ15 (Data input/output, word mode), A-1(LSB Address input, byte mode)
49
DQ14
I/O
15 Data inputs/outputs
47
DQ13
I/O
45
DQ12
I/O
42
DQ11
I/O
40
DQ10
I/O
38
DQ9
I/O
36
DQ8
I/O
50
DQ7
I/O
48
DQ6
I/O
46
DQ5
I/O
44
DQ4
I/O
41
DQ3
I/O
39
DQ2
I/O
37
DQ1
I/O
35
DQ0
I/O
32
CE#
I
Chip Enable input
34
OE#
I
Output Enable input
13
WE#
I
Write Enable input
16
WP#/ACC
I
Hardware Write Protect input/Programming Acceleration input
14
RESET#
I
Hardware Reset Pin input
53
BYTE#
I
Selects 8-bit or 16-bit mode
17
RY/BY#
O
Ready/Busy output
43
VCC
---
3.0 volt-only single power supply
29
VIO
O
Output Buffer power.
33, 52
VSS
---
Device Ground
27, 28, 30, 55,56
N.C
---
Pin not Connected Internally.
TU-X1E/RU
7 – 12
8. VHIAK8131C-1Y   CLOCK GENERATOR
9. VHILCX125FT-1Y  Quad Bus Buffer
Pin No.
Pin Name
I/O
Pin Function
1
X1
I
27.0MHz Crystal oscillator connection terminal
2
S0
 -
CLK1/CLK2/CLK3 output setting terminal.  Internal pull-up 360K
3
S1
 -
CLK1/CLK2/CLK3 output setting terminal.  Internal pull-up 360K
4
VIN
I
VCXO control voltage input terminal 
5
VDD1
 -
Power supply terminal 1
6
GND1
 -
Ground terminal 1
7
CLK1
O
Clock output terminal 1  Internal pull-down 510K
8
CLK2
O
Clock output terminal 2  Internal pull-down 510K
9
REFOUT
O
27.000MHz is outputted.
10
CLK3
O
Clock output terminal 3
11
CLK4
O
Clock output terminal 4
12
GND2
 -
Ground terminal 2
13
VDD2
 -
Power supply terminal 2
14
S2
 -
CLK1/CLK2/CLK3 output setting terminal.  Internal pull-up 360K
15
VDD3
 -
Power supply terminal 3
16
X2
O
27.0MHz Crystal oscillator connection terminal
Pin No.
Pin Name
I/O
Pin Function
1
1OE#
I
Invert output enable terminal 1
2
1A
I
Input terminal 1A
3
1Y
O
Output terminal 1Y
4
2OE#
I
Invert output enable terminal 2
5
2A
I
Input terminal 2A
6
2Y
O
Output terminal 2Y
7
GND
 -
Ground
8
3Y
O
Output terminal 3Y
9
3A
I
Input terminal 3A
10
3OE#
I
Invert output enable terminal 3
11
4Y
O
Output terminal 4Y
12
4A
I
Input terminal 4A
13
4OE#
I
Invert output enable terminal 4
14
VCC
 -
Power supply
TU-X1E/RU
7 – 13
10. VHIL6726A-1Y   PWM-CONTROL
11. VHIMP2367DE-1Y   STEPDOWN-CONV
Pin No.
Pin Name
I/O
Pin Function
1
BOOT
I
HS Driver Supply.
Connect through a capacitor (100nF) to the floating node (LS-Drain) pin
and provide necessary bootstrap diode from VCC.
2
UGATE
-
HS Driver Output. Connect to HS mosfet gate.
3
GND
I
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
4
LGATE/OC
I
LGATE. LS Driver Output. Connect to LS mosfet gate.
OC. Over Current threshold set. During a short period of time following
VCC rising over UVLO threshold, a 10
µA current is sourced from this pin.
Connect to GND with an ROCSET resistor greater than 5k
Ω to program OC 
Threshold. The resulting voltage at this pin is sampled and held internally as the 
OC set point. Maximum programmable OC threshold is 0.55V. 
A voltage greater than 0.75V (max) activates an internal clamp and causes
OC threshold to be set at 400 mV. 
ROCSET not connected sets the 400mV default threshold.
5
VCC
-
Device and LS Driver power supply.
Operative range from 4.1V to 13.2V. Filter with at least 1
µF MLCC to GND.
6
FB
I
Error Amplifier Inverting Input.
Connect with a resistor RFB to the output regulated voltage. Additional
resistor ROS to GND may be used to regulate voltages higher than the reference.
7
COMP/DIS
 
I
COMP. Error Amplifier Output. Connect with an RF - CF // CP to GND to
compensate the device control loop in conjunction to the FB pin.
During the Soft-Start phase, a 10
µA current is sourced from this pin so the
compensation capacitors also act to program the SS time.
DIS. The device can be disabled by pulling this pin lower than 0.4V (min).
Setting free the pin, the device enables again.
8
PHASE
I
HS Driver return path, current-reading and adaptive-dead-time monitor.   
Connect to the LS drain to sense RdsON drop to measure the output current.  
This pin is also used by the adaptive-dead-time control circuitry to monitor   
when HS mosfet is OFF.   
Pin No.
Pin Name
I/O
Pin Function
1
BS
I
High-Side gate drive boost input. BS supplies the drive for the high-side N-Channel 
MOSFET switch. Connect a 0.01
µF or greater capacitor from SW to BS to power the 
high-side switch.
2
IN
 
-
Power input. IN supplies the power to the IC, as well as the step-down converter 
switches. Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suit-
ably large capacitor to eliminate noise on the input to the IC. 
3
SW
O
Power switching output. SW is the switching node that supplies power to the output. 
Connect the output LC filter from SW to the output load. Note that a capacitor is 
required from SW to BS to power the high-side switch.
4
GND
 -
Ground
5
FB
I
Feedback input. FB senses the output voltage to regulate that voltage. Drive FB with a 
resistive voltage driver from the output voltage. The feedback reference voltage is 
0.795V. 
6
FB
I
Compensation Node. COMP is used to compensate the regulation control loop. Con-
nect a series RC network from COMP to GND to compensate the regulation control 
loop. In side cases, an additional capacitor from COMP to GND is required.
7
EN
I
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN higher 
than 2.7V to turn on the regulator, drive it lower than 1.1V to turn it off . Pull up with 
100K resister for automatic startup.
8
SS
I
Soft-start control input. SS control the soft-start period. Connect a capacitor from SS 
to GND to set the soft-start period. 
TU-X1E/RU
7 – 14
12. RH-IXC187WJQZQ   512Mbit DDR2 SDRAM
Pin No.
Pin Name
I/O
Pin Function
45,46
CK, CK
I
Clock: CK and CK# are differential clock inputs. 
All adress and control input signals are sampled on the positive edge of CK and nega-
tive edge of CK#. 
Output (read) data is referenced to the both edges of CK. Internal clock signals are 
derived from CK/CK#
44
CKE
I
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers. 
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all 
banks idle), or Active Power-Down (row Active in any bank). 
CKE is synchronous for power down entry and exit, and for self refresh entry. 
CKE is asynchronous for self refresh exit, and and for output disable. 
CKE must be maintained high throughout Read and Write accesses. 
Input buffers, excluding CK, CK# and CKE are disabled during Power-Down. 
Input buffers, excluding CKE, are disabled during Self Refresh.
24
CS
I
Chip Select: CS# enables (resistered LOW) and disables (resistered HIGH) the com-
mand decoder. 
All commands are masked when CS# is resisters HIGH. 
CS# provides for external bank selection on system with multiple banks. 
CS# is considered part of the command code.
23,22,21
RAS, CAS, WE
I
Command Inputs: RAS, CAS and WE (along with CS) define the command being 
entered.
20, 49
LDM,UDM
I
Input Data Mask: DM is an input mask signal for write data. 
Input data is masked when DM is sampled HIGH along with that input data during a 
WRITE access. 
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
26, 27
BA0 - BA1
I
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE 
or PRECHARGE command is being applied. 
28, 29, 30, 31, 
32, 35, 36, 37, 
38, 39, 40, 41, 42
A [0:12]
I
Address Inputs: Provided the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the PRE-
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). 
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during MODE REGISTER SET com-
mands.
BA0 and BA1 define which mode register is loaded during the MODE RESISTER SET 
command (MRS or EMRS).
2, 4, 5, 7, 8, 10, 
11, 13, 54, 56, 57, 
59, 60, 62, 63, 65
DQ
I/O
Data Input/ Output:  Data bus.
16,
51
LDQS,
UDQS,
I/O
Data Strobe: output with read data, input with write data. Edge-aligned with read data, 
centered in write data. Used to capture write data. 
For the *16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the 
data on DQ8-DQ15. 
LDQS is NC on *4 and *8.
14, 17, 19, 25, 
43, 50, 53
NC
 -
No Connect: No internal electrical connection is present.
3, 9, 15, 55, 61
VDDQ
 -
DQ Power Supply: 2.5V 
± 0.2V.
6, 12, 52, 58, 64
VSSQ
 -
DQ Ground.
1, 18, 33
VDD
 -
Power Supply: 2.5V 
± 0.2V.
34,48,66
VSS
 -
Ground.
49
VREF
 -
SSTL_2 reference voltage.
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