View Sharp PZ-50MR2E (serv.man8) Service Manual online
This IC is a 7-input, 3-output selector.
The video signals other than those for the PC, components and RGB input, which have been input from each input
connector and the tuner, and all the audio signals are sent to the IC1301 and then selected.
Output 1 is used internally and output 3 in the monitor output.
When the S video input is output to the monitor, Y and C signals are mixed in this IC.
The video signals sent to the IC1301 are then input to the YC separation circuits, IC405 (main) and IC402 (sub).
The audio signals are input to the PC I/F Unit via IC2501 (sound processor).
This IC is a 4-input, 8-output video selector for component input.
The AV3 component input, AV1, RGB input, and Teletext RGB signals are input to the IC1401. The output signals
go to the main, sub, and component channels.
This IC is a microprocessor for Teletext.
Video signals are input to the IC1601, which then decodes the Teletex data and outputs it as RGB data.
This IC is used to decode audio signals.
It serves as both the S IF decoder and the selector for the input audio data.
This IC synchronizes video and chroma signals for PAL/NTSC/SECAM colour televisions.
Its video circuit includes a high-performance image quality compensation circuit and its chroma circuit a PAL/
NTSC/SECAM automatic selection circuit. The PAL-M/N clock signals at 4.43 and 8.58 MHz are internally generated
for colour demodulation.
The PAL/SECAM demodulation circuit uses a base band signal processing system with built-in IH DL and is
The IC801/IC802 has 4 lines for YC signal input, 2 lines for RGB signal input, and 2 lines for colour difference
signal input. It receives colour different signals for the main and sub channels from IC405 (main), IC402 (sub), and
IC1401 in the former stage, and provides 1 line for colour difference signal output.
This IC consists of a base band signal processing section for colour different input, an RGB signal processing
section, and a 4-line video switch (including HV synchronizing signal processing).
Input selection is performed by INPUT-SEL (I
As the multi-scanning compliance range, a horizontal scanning frequency of 15~60 kHz can be input.
This IC is FPGA for the synchronizing system.
It creates sand castle pulses for IC803 and generates horizontal blanking signals.
This IC synchronizes TV component signals.
The IC804 incorporates the necessary functions for measuring the frequency of input signals and synchronous
replay into a single chip, and is applicable for horizontal synchronous replay (15.75, 31.5, 33.75, and 45 kHz) and
vertical synchronous replay (525I, 525P, 625I, 750P, 1125I, 1125P, PAL 100 Hz, and NTSC 120 Hz).
This IC is a comb filter in the applicable field for both the NTSC and PAL systems. It performs the Y/C separation
of the main and sub channel video signals that have been output from IC1801.
This IC is a 6.7 MHz low-pass filter.
This IC is a 6.7 MHz low-pass filter incorporating a 6 dB amplifier.
This IC is a 30 MHz low-pass filter incorporating a 6 dB amplifier.
This IC is designed to control the 6-channel PWM switching regulator.
With 5 step-up switching regulator lines incorporated, the IC converts +10V to +2.5V, +3.3V and +5.8V.
Also with a step-down switching regulator line incorporated, the IC converts +10V to +6.0V, -5.0V, +12V and +35V.
The lines are individually turned on and off.
This IC is an A/D converter that incorporates a 3-channel, 8-bit, 120 MSPS amplifier and PLL. It is used for the
video signals input to the PC I/F unit on the main channel in the 1-screen and 2-screen modes, and also for the
video signals input from the front for the PC.
The video signals (analog RGB) from the CN6 are input to IN1 of IC4.
For the PC, the video signals (analog RGB) from CN8 are input to IN2 of IC4.
The input video signals are converted into digital signals and then sent to IC25.
This IC is a 3-channel, 8-bit, 20 MSPS A/D converter.
It is used for the sub-channel of the video signals input to the PC I/F Unit in the 2-screen mode.
The video signals (analog Y, Cb, Cr) from CN6 are input to IC310.
The video signals input to this IC are converted into digital signals and then sent to IC25.
This IC performs the I/P conversion and scaling to match the digitalized video with the output resolution, and also
the data conversion.
It has two input lines, V0 and V1. The V0 line is used to process the RGB, composite, and skirt signals input to the
480i and 580i components for the sub-channel in the 2-screen mode. The V1 line is used to process all the signals
as well as V1 for the main channel in the 1-screen and 2-screen modes.
The IC25 detects what resolution is input from the input synchronizing signal; creates H synchronization in
accordance with the frequency division ratio; creates the clamp signal in accordance with the input synchronizing
signal; and performs the data matrix conversion.
The video signals input to this IC is sent to IC413.
This IC is a panel link transmitter.
It converts the 8-bit RGB video data output from IC25 into the differential TMDS signals and then digitally transmits
the converted signals to the monitor.
The TMDS signals are transmitted at the frequency 10 times higher than the clock frequency.
This IC is a 1-chip RISC microprocessor.
It performs communication with the monitor and operates the system.
The IC1 also controls each IC in the AVC system and partially manages the power source.
This IC is an RS-232 line driver receiver conforming to the EIA/TIA-232-E standard.
The IC405, when connected to a PC, allows for externally controlling the system.
It is also applicable for upgrading IC1.
Composite video signal input
YIN1 to feed in the Y/C-separated signal of VOUT1 output.
CIN1 to feed in the Y/C-separated signal of VOUT1 output.
luminance signal output by I2C Bus control.
Video signal output terminal for luminance signal output.
below 1.3V. 4:3 letterbox signal when between 1.3V and 2.5V. 16:9 image squeeze
signal when above 2.5V. To be pulled down to GDN at 100K
Used to switch between composite video and S signals. Detection results to be written
in status register. S signal when below 3.5V. Composite video signal when above 3.5V.
To be pulled up to 5V at 100K
90H also when the terminal is open.
I2C Bus signal input terminal.
I2C Bus signal input terminal.
Used to feed out S2-compatible DC level to be superimposed on COUT3 output. DC to
be superimposed by connecting to COUT3 output via a capacitor. Control to be made
by I2C Bus. S2-specified output impedance of 10 ±3K
2.5V. Mute off when the terminal is open.
Internal reference bias (Vcc/2) terminal. To be connected to GND with a capacitor in